A measure of how many of the operations in a computer program can be performed simultaneously.
Published in Chapter:
Simultaneous MultiThreading Microarchitecture
Chen Liu (Florida International University, USA), Xiaobin Li (Intel Corporation, USA), Shaoshan Liu (University of California at Irvine, USA), and Jean-Luc Gaudiot (University of California at Irvine, USA)
Copyright: © 2010
|Pages: 31
DOI: 10.4018/978-1-60566-661-7.ch024
Abstract
Due to the conventional sequential programming model, the Instruction-Level Parallelism (ILP) that modern superscalar processors can explore is inherently limited. Hence, multithreading architectures have been proposed to exploit Thread-Level Parallelism (TLP) in addition to conventional ILP. By issuing and executing instructions from multiple threads at each clock cycle, Simultaneous MultiThreading (SMT) achieves some of the best possible system resource utilization and accordingly higher instruction throughput. In this chapter, the authors describe the origin of SMT microarchitecture, comparing it with other multithreading microarchitectures. They identify several key aspects for high-performance SMT design: fetch policy, handling long-latency instructions, resource sharing control, synchronization and communication. They also describe some potential benefits of SMT microarchitecture: SMT for faulttolerance and SMT for secure communications. Given the need to support sequential legacy code and emerge of new parallel programming model, we believe SMT microarchitecture will play a vital role as we enter the multi-thread multi/many-core processor design era.