The set of special registers incorporated in modern CPU chipsets that serve the purpose of tracking the performance of low-level operational events as they execute at processor cores, cache memory, main memory and Input/Output stages of server hardware.
Published in Chapter:
Quality of Service Monitoring Strategies in Service Oriented Architecture Environments using Processor Hardware Performance Metrics
Ernest Sithole (University of Ulster at Coleraine, UK), Sally McClean (University of Ulster at Coleraine, UK), Bryan Scotney (University of Ulster at Coleraine, UK), Gerard Parr (University of Ulster at Coleraine, UK), Adrian Moore (University of Ulster at Coleraine, UK), Dave Bustard (University of Ulster at Coleraine, UK), and Stephen Dawson (SAP Research Belfast, UK)
Copyright: © 2012
|Pages: 29
DOI: 10.4018/978-1-61350-432-1.ch005
Abstract
The sharp growth in data-intensive applications such as social, professional networking and online commerce services, multimedia applications, as well as the convergence of mobile, wireless, and internet technologies, is greatly influencing the shape and makeup of on-demand enterprise computing environments. In response to the global needs for on-demand computing services, a number of trends have emerged, one of which is the growth of computing infrastructures in terms of the number of computing node entities and the widening in geophysical distributions of deployed node elements. Another development has been the increased complexity in the technical composition of the business computing space due to the diversity of technologies that are employed in IT implementations. Given the huge scales in infrastructure sizes and data handling requirements, as well as the dispersion of compute nodes and technology disparities that are associated with emerging computing infrastructures, the task of quantifying performance for capacity planning, Service Level Agreement (SLA) enforcements, and Quality of Service (QoS) guarantees becomes very challenging to fulfil. In order to come up with a viable strategy for evaluating operational performance on computing nodes, we propose the use of on-chip registers called Performance Monitoring Counters (PMCs), which form part of the processor hardware. The use of PMC measurements is largely non-intrusive and highlights performance issues associated with runtime execution on the CPU hardware architecture. Our proposed strategy of employing PMC data thus overcomes major shortcomings of existing benchmarking approaches such as overheads in the software functionality and the inability to offer detailed insight into the various stages of CPU and memory hardware operation.