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What is RTL

Handbook of Research on Power and Energy System Optimization
( Register Transfer Level): Is a high level description which models a synchronous circuit in terms of the flow of digital signals between hardware registers, and the logical operations performed on those signals.
Published in Chapter:
Optimization of Dynamic Power for System on Programmable Chip SOPC: Power Optimization
Mehdi Jemai (University of Monastir, Tunisia), Siwar Ben Haj Hassine (National School of Engineers of Sousse, Tunisia), Bouraoui Ouni (National School of Engineers of Sousse, Tunisia), and Abdellatif Mtibaa (University of Monastir, Tunisia)
Copyright: © 2018 |Pages: 30
DOI: 10.4018/978-1-5225-3935-3.ch017
Abstract
In this chapter, the authors present a new scheduling algorithm that brings a reduction in dynamic power consumption by achieving components scheduling while holding the global latency of the application. The main idea of that algorithm is to augment the latency of some components without impacting the dependency constraint and degrading the global latency of the system. There exist many solutions that manage to increase component's latency; one of them is through decreasing the frequency of their corresponding clocks. Generally, such a method leads to an augmentation in global latency of a system. However, this algorithm manages to reduce the consumed power and hold the same global latency of the system. The presented algorithm has been tested and it provides a significant gain in power at both simulation and physical levels.
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More Results
High Level Design Approach for FPGA Implementation of ANNs
Acronym of Register Transfer Level
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Real-Time Image and Video Processing Using High-Level Synthesis (HLS)
(Register Transfer Level) is a design method that models digital circuits in terms of the flow of data between hardware registers.
Full Text Chapter Download: US $37.50 Add to Cart
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