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What is SMP node

Chapter 1
Handbook of Research on Computational Science and Engineering: Theory and Practice
one or more sockets interconnected such that all cores on all sockets have access to each other memory modules
Published in Chapter:
Hardware Trends and Implications for Programming Models
Gabriele Jost (The University of Texas at Austin, USA) and Alice E. Koniges (Lawrence Berkeley National Laboratory, USA)
Copyright: © 2012 |Pages: 21
DOI: 10.4018/978-1-61350-116-0.ch001
Abstract
The upcoming years bring new challenges in high-performance computing (HPC) technology. Fundamental changes in the building blocks of HPC hardware are forcing corresponding changes in programming models to effectively use these new architectures. The changes in store for HPC will rival the vector to massively parallel transition that scientific and engineering codes and methodologies endured several years ago. We describe some of the upcoming trends in hardware designs, and suggest ways in which software and programming models will advance accordingly.
Full Text Chapter Download: US $37.50 Add to Cart
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Chapter 1
Hardware Trends and Implications for Programming Models
one or more sockets interconnected such that all cores on all sockets have access to each other memory modules
Published in Chapter: Hardware Trends and Implications for Programming Models; From: Handbook of Research on Computational Science and Engineering: Theory and Practice
Full Text Chapter Download: US $37.50 Add to Cart
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