Time slack, or slack margin, or just slack, is an available time margin left unused in a clock period, that is, the difference between the clock period and the longest path delay, or critical path delay, in a sequential circuit.
Published in Chapter:
Ultra-Low-Power Strategy for Reliable IoE Nanoscale Integrated Circuits
Jorge Semião (University of Algarve, Portugal), Ruben Cabral (University of Algarve, Portugal), Hugo Cavalaria (University of Algarve, Portugal), Marcelino Santos (University of Algarve, Portugal), Isabel C. Teixeira (University of Algarve, Portugal), and J. Paulo Teixeira (University of Algarve, Portugal)
Copyright: © 2019
|Pages: 26
DOI: 10.4018/978-1-5225-7332-6.ch011
Abstract
Ultra-low-power strategies have a huge importance in today's integrated circuits designed for internet of everything (IoE) applications, as all portable devices quest for the never-ending battery life. Dynamic voltage and frequency scaling techniques can be rewarding, and the drastic power savings obtained in subthreshold voltage operation makes this an important technique to be used in battery-operated devices. However, unpredictability in nanoscale chips is high, and working at reduced supply voltages makes circuits more vulnerable to operational-induced delay-faults and transient-faults. The goal is to implement an adaptive voltage scaling (AVS) strategy, which can work at subthreshold voltages to considerably reduce power consumption. The proposed strategy uses aging-aware local and global performance sensors to enhance reliability and fault-tolerance and allows circuits to be dynamically optimized during their lifetime while prevents error occurrence. Spice simulations in 65nm CMOS technology demonstrate the results.