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Design of a Power Aware Systolic Array based Support Vector Machine Classifier

Design of a Power Aware Systolic Array based Support Vector Machine Classifier

Bhaswati Mandal, Manash Pratim Sarma, Kandarpa Kumar Sarma
Copyright: © 2015 |Pages: 43
ISBN13: 9781466684935|ISBN10: 1466684933|EISBN13: 9781466684942
DOI: 10.4018/978-1-4666-8493-5.ch005
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MLA

Mandal, Bhaswati, et al. "Design of a Power Aware Systolic Array based Support Vector Machine Classifier." Intelligent Applications for Heterogeneous System Modeling and Design, edited by Kandarpa Kumar Sarma, et al., IGI Global, 2015, pp. 96-138. https://doi.org/10.4018/978-1-4666-8493-5.ch005

APA

Mandal, B., Sarma, M. P., & Sarma, K. K. (2015). Design of a Power Aware Systolic Array based Support Vector Machine Classifier. In K. Sarma, M. Sarma, & M. Sarma (Eds.), Intelligent Applications for Heterogeneous System Modeling and Design (pp. 96-138). IGI Global. https://doi.org/10.4018/978-1-4666-8493-5.ch005

Chicago

Mandal, Bhaswati, Manash Pratim Sarma, and Kandarpa Kumar Sarma. "Design of a Power Aware Systolic Array based Support Vector Machine Classifier." In Intelligent Applications for Heterogeneous System Modeling and Design, edited by Kandarpa Kumar Sarma, Manash Pratim Sarma, and Mousmita Sarma, 96-138. Hershey, PA: IGI Global, 2015. https://doi.org/10.4018/978-1-4666-8493-5.ch005

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Abstract

This chapter presents a method for generating binary and multiclass Support Vector Machine (SVM) classifier with multiplierless kernel function. This design provides reduced power, area and reduced cost due to the use of multiplierless kernel operation. Binary SVM classifier classifies two groups of linearly or nonlinearly separable data while the multiclass classification provides classification of three nonlinearly separable data. Here, at first SVM classifier is trained for different classification problems and then the extracted training parameters are used in the testing phase of the same. The dataflow from all the processing elements (PEs) are parallely supported by systolic array. This systolic array architecture provides faster processing of the whole system design.

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