Welcome to the InfoSci Platform
An All-Inversion-Region gm/ID Based Design Methodology for Radiofrequency Blocks in CMOS Nanometer Technologies

An All-Inversion-Region gm/ID Based Design Methodology for Radiofrequency Blocks in CMOS Nanometer Technologies

Rafaella Fiorelli, Eduardo Peralías, Fernando Silveira
Copyright: © 2014 |Pages: 24
ISBN13: 9781466651258|ISBN10: 1466651253|EISBN13: 9781466651265
DOI: 10.4018/978-1-4666-5125-8.ch038
Cite Chapter Cite Chapter

MLA

Fiorelli, Rafaella, et al. "An All-Inversion-Region gm/ID Based Design Methodology for Radiofrequency Blocks in CMOS Nanometer Technologies." Nanotechnology: Concepts, Methodologies, Tools, and Applications, edited by Information Resources Management Association, IGI Global, 2014, pp. 874-897. https://doi.org/10.4018/978-1-4666-5125-8.ch038

APA

Fiorelli, R., Peralías, E., & Silveira, F. (2014). An All-Inversion-Region gm/ID Based Design Methodology for Radiofrequency Blocks in CMOS Nanometer Technologies. In I. Management Association (Ed.), Nanotechnology: Concepts, Methodologies, Tools, and Applications (pp. 874-897). IGI Global. https://doi.org/10.4018/978-1-4666-5125-8.ch038

Chicago

Fiorelli, Rafaella, Eduardo Peralías, and Fernando Silveira. "An All-Inversion-Region gm/ID Based Design Methodology for Radiofrequency Blocks in CMOS Nanometer Technologies." In Nanotechnology: Concepts, Methodologies, Tools, and Applications, edited by Information Resources Management Association, 874-897. Hershey, PA: IGI Global, 2014. https://doi.org/10.4018/978-1-4666-5125-8.ch038

Export Reference

Mendeley
Favorite

Abstract

This chapter presents a design optimization methodology for analog radiofrequency (RF) blocks based on the gm/ID technique and on the exploration of all-inversion regions (from weak inversion or sub-threshold to strong inversion or above threshold) of the MOS transistor in nanometer technologies. The use of semi-empirical models of MOS transistors and passive components, as inductors or capacitors, assures accurate designs, reducing time and efforts for transferring the initial block specifications to a compliant design. This methodology permits the generation of graphical maps to visualize the evolution of the circuit characteristics when sweeping both the inversion zone and the bias current, allowing reaching very good compromises between performance aspects of the circuit (e.g. noise and power consumption) for a set of initial specifications. In order to demonstrate the effectiveness of this methodology, it is applied in the design of two basic blocks of RF transceivers: low noise amplifiers (LNAs) and voltage controlled oscillators (VCOs), implemented in two different nanometer technologies and specified to be part of a 2.4 GHz transceiver. A possible design flow of each block is provided; resulting designs are implemented and verified both with simulations and measurements.

Request Access

You do not own this content. Please login to recommend this title to your institution's librarian or purchase it from the IGI Global bookstore.