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Implementation of Improved Hash and Mapping Modified Low Power Parallel Bloom Filter Design

Implementation of Improved Hash and Mapping Modified Low Power Parallel Bloom Filter Design

K. Saravanan, A. Senthilkumar
Copyright: © 2013 |Volume: 7 |Issue: 4 |Pages: 11
ISSN: 1930-1650|EISSN: 1930-1669|EISBN13: 9781466635432|DOI: 10.4018/ijisp.2013100102
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MLA

Saravanan, K., and A. Senthilkumar. "Implementation of Improved Hash and Mapping Modified Low Power Parallel Bloom Filter Design." IJISP vol.7, no.4 2013: pp.11-21. http://doi.org/10.4018/ijisp.2013100102

APA

Saravanan, K. & Senthilkumar, A. (2013). Implementation of Improved Hash and Mapping Modified Low Power Parallel Bloom Filter Design. International Journal of Information Security and Privacy (IJISP), 7(4), 11-21. http://doi.org/10.4018/ijisp.2013100102

Chicago

Saravanan, K., and A. Senthilkumar. "Implementation of Improved Hash and Mapping Modified Low Power Parallel Bloom Filter Design," International Journal of Information Security and Privacy (IJISP) 7, no.4: 11-21. http://doi.org/10.4018/ijisp.2013100102

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Abstract

In this article, the authors present an investigation on bloom filters and introduce a new improved variant, which uses a secure modified hash function and suggested improved mapping scheme with an efficient parallel architecture. This novel architecture provides efficient, relatively fast membership querying and compact information representation with negligible false positive. This is relatively a low power and secure design with very less false positive ratio when compared with the traditional bloom filters. The design has been evaluated and tested using Xilinx 65 nm Virtex-5 field-programmable gate array as the target technology. The performance matrices are false positive ratio, power, speed and compactness.

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