Low Power Arithmetic Circuit Design for Multimedia Applications

Low Power Arithmetic Circuit Design for Multimedia Applications

Senthil C. Pari
Copyright: © 2016 |Pages: 31
ISBN13: 9781522501909|ISBN10: 1522501908|EISBN13: 9781522501916
DOI: 10.4018/978-1-5225-0190-9.ch010
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MLA

Pari, Senthil C. "Low Power Arithmetic Circuit Design for Multimedia Applications." Design and Modeling of Low Power VLSI Systems, edited by Manoj Sharma, et al., IGI Global, 2016, pp. 252-282. https://doi.org/10.4018/978-1-5225-0190-9.ch010

APA

Pari, S. C. (2016). Low Power Arithmetic Circuit Design for Multimedia Applications. In M. Sharma, R. Gautam, & M. Khan (Eds.), Design and Modeling of Low Power VLSI Systems (pp. 252-282). IGI Global. https://doi.org/10.4018/978-1-5225-0190-9.ch010

Chicago

Pari, Senthil C. "Low Power Arithmetic Circuit Design for Multimedia Applications." In Design and Modeling of Low Power VLSI Systems, edited by Manoj Sharma, Ruchi Gautam, and Mohammad Ayoub Khan, 252-282. Hershey, PA: IGI Global, 2016. https://doi.org/10.4018/978-1-5225-0190-9.ch010

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Abstract

The objective of this chapter is to describe the various designed arithmetic circuit for an application of multimedia circuit that can be used in a high-performance or mobile microprocessor with a particular set of optimisation criteria. The aim of this chapter is to describe the design method of binary arithmetic especially using by CMOS and Pass Transistor Logic technique. The pass transistor techniques are reduced the noise margin for small circuit, which can be explained in this chapter. This chapter further describe the types of arithmetic and its techniques. The technique design principle procedure should make the following decisions: circuit family (complementary static CMOS, pass-transistor, or Shannon Theorem based); type of arithmetic to be used. The decisions on the designed logic level significantly affect the propagation delay, area and power dissipation.

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