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Hardware Acceleration of CBIR System with FPGA-Based Platform

Hardware Acceleration of CBIR System with FPGA-Based Platform

Veronica Gil-Costa, Romina Soledad Molina, Ricardo Petrino, Carlos Federico Sosa Paez, A. Marcela Printista, Julio Daniel Dondo Gazzano
Copyright: © 2016 |Pages: 33
ISBN13: 9781522502999|ISBN10: 1522502998|EISBN13: 9781522503002
DOI: 10.4018/978-1-5225-0299-9.ch007
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MLA

Gil-Costa, Veronica, et al. "Hardware Acceleration of CBIR System with FPGA-Based Platform." Field-Programmable Gate Array (FPGA) Technologies for High Performance Instrumentation, edited by Julio Daniel Dondo Gazzano, et al., IGI Global, 2016, pp. 138-170. https://doi.org/10.4018/978-1-5225-0299-9.ch007

APA

Gil-Costa, V., Molina, R. S., Petrino, R., Paez, C. F., Printista, A. M., & Gazzano, J. D. (2016). Hardware Acceleration of CBIR System with FPGA-Based Platform. In J. Gazzano, M. Crespo, A. Cicuttin, & F. Calle (Eds.), Field-Programmable Gate Array (FPGA) Technologies for High Performance Instrumentation (pp. 138-170). IGI Global. https://doi.org/10.4018/978-1-5225-0299-9.ch007

Chicago

Gil-Costa, Veronica, et al. "Hardware Acceleration of CBIR System with FPGA-Based Platform." In Field-Programmable Gate Array (FPGA) Technologies for High Performance Instrumentation, edited by Julio Daniel Dondo Gazzano, et al., 138-170. Hershey, PA: IGI Global, 2016. https://doi.org/10.4018/978-1-5225-0299-9.ch007

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Abstract

Typical applications involving image retrieval processes demand a great amount of computation. The visual content of the images is extracted and represented by means of descriptor vectors of multidimensional characteristics. The image retrieval process consists of two tasks: (1) generation of database and indexing; and (2) the search process. The first task involves the construction of descriptor vectors. Then, an index is built upon the database to speed the search process. The second requires calculating a descriptor vector for the query image and computes the similarity search with the ones stored in the index. In this context, it is relevant to devise new algorithms and different parallel platforms that can reduce execution times. In particular, this work focuses on platforms with FPGAs based SoCs to present and evaluate a two stage system where the index is constructed off-line and the similarity search is executed on-line. Results show that the FPGA is 73% faster than a 2 Quad CPU to compute the descriptor vector of an image when using the Color Layout Descriptor of MPEG-7.

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