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Viterbi Decoder in Hardware

Viterbi Decoder in Hardware

Mário Pereira Véstias
Copyright: © 2018 |Pages: 12
ISBN13: 9781522522553|ISBN10: 1522522557|EISBN13: 9781522522560
DOI: 10.4018/978-1-5225-2255-3.ch549
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MLA

Véstias, Mário Pereira. "Viterbi Decoder in Hardware." Encyclopedia of Information Science and Technology, Fourth Edition, edited by Mehdi Khosrow-Pour, D.B.A., IGI Global, 2018, pp. 6307-6318. https://doi.org/10.4018/978-1-5225-2255-3.ch549

APA

Véstias, M. P. (2018). Viterbi Decoder in Hardware. In M. Khosrow-Pour, D.B.A. (Ed.), Encyclopedia of Information Science and Technology, Fourth Edition (pp. 6307-6318). IGI Global. https://doi.org/10.4018/978-1-5225-2255-3.ch549

Chicago

Véstias, Mário Pereira. "Viterbi Decoder in Hardware." In Encyclopedia of Information Science and Technology, Fourth Edition, edited by Mehdi Khosrow-Pour, D.B.A., 6307-6318. Hershey, PA: IGI Global, 2018. https://doi.org/10.4018/978-1-5225-2255-3.ch549

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Abstract

Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is the most well known trellis-based maximum likelihood decoding algorithm. The Viterbi algorithm is executed by a Viterbi decoder. Different hardware solutions may be considered to implement a Viterbi decoder with different design requirements in terms of area, performance, power consumption, among others. The most appropriate solution depends on the metric requirements of the application as well as on the target technology. Properties of the Viterbi algorithm are used to simplify and improve the architecture of the Viterbi decoder. In particular, statistical properties of the Viterbi algorithm are used to design parallel Viterbi decoders with very high data decoding rates. The article focuses on the implementation of a Viterbi decoder in hardware, including optimizations to improve the area and performance.

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