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High Level Transformation Techniques for Designing Reliable and Secure DSP Architectures

High Level Transformation Techniques for Designing Reliable and Secure DSP Architectures

Jyotirmoy Pathak, Abhishek Kumar, Suman Lata Tripathi
Copyright: © 2020 |Pages: 11
ISBN13: 9781799814641|ISBN10: 1799814645|ISBN13 Softcover: 9781799814658|EISBN13: 9781799814665
DOI: 10.4018/978-1-7998-1464-1.ch009
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MLA

Pathak, Jyotirmoy, et al. "High Level Transformation Techniques for Designing Reliable and Secure DSP Architectures." AI Techniques for Reliability Prediction for Electronic Components, edited by Cherry Bhargava, IGI Global, 2020, pp. 164-174. https://doi.org/10.4018/978-1-7998-1464-1.ch009

APA

Pathak, J., Kumar, A., & Tripathi, S. L. (2020). High Level Transformation Techniques for Designing Reliable and Secure DSP Architectures. In C. Bhargava (Ed.), AI Techniques for Reliability Prediction for Electronic Components (pp. 164-174). IGI Global. https://doi.org/10.4018/978-1-7998-1464-1.ch009

Chicago

Pathak, Jyotirmoy, Abhishek Kumar, and Suman Lata Tripathi. "High Level Transformation Techniques for Designing Reliable and Secure DSP Architectures." In AI Techniques for Reliability Prediction for Electronic Components, edited by Cherry Bhargava, 164-174. Hershey, PA: IGI Global, 2020. https://doi.org/10.4018/978-1-7998-1464-1.ch009

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Abstract

Reverse engineering (RE) has become a serious threat to the silicon industry. To overcome this threat, the ICs need to be made secure and non-obvious in order to find their functionality with their architecture. Real-time signal processing algorithms need to be faster and more reliable. Adding up additional circuits for increasing the security of the IC is not permittable due to increase in overhead of the IC. In this chapter, the authors introduce a few high-level transformations (HLT) that are used to make the circuit more reliable and secure against the reverse engineering without having overhead on the IC.

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