Low Power, High Performance CNTFET-Based SRAM Cell Designs: Design and Analysis of 6T CNTFET SRAM Cells

Low Power, High Performance CNTFET-Based SRAM Cell Designs: Design and Analysis of 6T CNTFET SRAM Cells

B. K. Madhavi, Rajendra Prasad Somineni
ISBN13: 9781799813934|ISBN10: 1799813932|EISBN13: 9781799813958
DOI: 10.4018/978-1-7998-1393-4.ch006
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MLA

Madhavi, B. K., and Rajendra Prasad Somineni. "Low Power, High Performance CNTFET-Based SRAM Cell Designs: Design and Analysis of 6T CNTFET SRAM Cells." Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET), edited by Balwinder Raj, et al., IGI Global, 2020, pp. 93-128. https://doi.org/10.4018/978-1-7998-1393-4.ch006

APA

Madhavi, B. K. & Somineni, R. P. (2020). Low Power, High Performance CNTFET-Based SRAM Cell Designs: Design and Analysis of 6T CNTFET SRAM Cells. In B. Raj, M. Khosla, & A. Singh (Eds.), Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET) (pp. 93-128). IGI Global. https://doi.org/10.4018/978-1-7998-1393-4.ch006

Chicago

Madhavi, B. K., and Rajendra Prasad Somineni. "Low Power, High Performance CNTFET-Based SRAM Cell Designs: Design and Analysis of 6T CNTFET SRAM Cells." In Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET), edited by Balwinder Raj, Mamta Khosla, and Amandeep Singh, 93-128. Hershey, PA: IGI Global, 2020. https://doi.org/10.4018/978-1-7998-1393-4.ch006

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Abstract

The main objective of this chapter is to provide high-performance, low-power solutions for VLSI system designers. As technology scales down to 32nm and below, the present CMOS technology has to face the scaling limit, such as the increased leakage power, SCEs, and so on. To overcome these limits, the researchers have experimented on other technologies, among which a CNT technology-based device called CNTFET has been evaluated as one of the promising replacements to CMOS technology. In any digital systems, memory is an integral part, and it is also the largest constituent. SRAM is a widely used memory. In today's ICs, SRAM is going to occupy 60-70% of the total chip area. In this connection, this chapter describes the design of CNTFET-based 6T SRAM cell using circuit-level leakage reduction techniques, named sleep transistor, forced stack, data-retention sleep transistor, and stacked sleep.

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