Welcome to the InfoSci Platform
Improving the Lifetime of Phase Change Memory by Shadow Dynamic Random Access Memory

Improving the Lifetime of Phase Change Memory by Shadow Dynamic Random Access Memory

Bhukya Krishna Priya, N. Ramasubramanian
Copyright: © 2021 |Volume: 12 |Issue: 2 |Pages: 15
ISSN: 1947-959X|EISSN: 1947-9603|EISBN13: 9781799860914|DOI: 10.4018/IJSSMET.2021030109
Cite Article Cite Article

MLA

Priya, Bhukya Krishna, and N. Ramasubramanian. "Improving the Lifetime of Phase Change Memory by Shadow Dynamic Random Access Memory." IJSSMET vol.12, no.2 2021: pp.154-168. http://doi.org/10.4018/IJSSMET.2021030109

APA

Priya, B. K. & Ramasubramanian, N. (2021). Improving the Lifetime of Phase Change Memory by Shadow Dynamic Random Access Memory. International Journal of Service Science, Management, Engineering, and Technology (IJSSMET), 12(2), 154-168. http://doi.org/10.4018/IJSSMET.2021030109

Chicago

Priya, Bhukya Krishna, and N. Ramasubramanian. "Improving the Lifetime of Phase Change Memory by Shadow Dynamic Random Access Memory," International Journal of Service Science, Management, Engineering, and Technology (IJSSMET) 12, no.2: 154-168. http://doi.org/10.4018/IJSSMET.2021030109

Export Reference

Mendeley
Favorite Full-Issue Download

Abstract

Emerging NVM are replacing the conventional memory technologies due to their huge cell density and low energy consumption. Restricted writes is one of the major drawbacks to adopt PCM memories in real-time environments. The non-uniform writes and process variations can damage the memory cell with intensive writes, as PCM memory cells are having restricted write endurance. To prolong the lifetime of a PCM, an extra DRAM shadow memory has been added to store the writes that comes to the PCM and to level out the wearing that occurs on the PCM. An extra address directory will store the address of data written to the DRAM and a counter is used to count the number of times the blocks are written into. Based upon the counter values, the data will be written from DRAM to the PCM. The data is written to the DRAM from the PCM, based on the data requirement. Experimental results show the reduction in overall writes in a PCM, which in turn improves the lifetime of a PCM by 5% with less hardware and power overhead.

Request Access

You do not own this content. Please login to recommend this title to your institution's librarian or purchase it from the IGI Global bookstore.