Welcome to the InfoSci Platform
Design of Efficient VLSI Architecture and Implementation of Power-Optimized Turbo Decoder for LTE Networks

Design of Efficient VLSI Architecture and Implementation of Power-Optimized Turbo Decoder for LTE Networks

Manjunatha K. N., Raghu N., Kiran B.
Copyright: © 2023 |Pages: 36
ISBN13: 9781668453766|ISBN10: 1668453762|ISBN13 Softcover: 9781668453773|EISBN13: 9781668453780
DOI: 10.4018/978-1-6684-5376-6.ch006
Cite Chapter Cite Chapter

MLA

Manjunatha K. N., et al. "Design of Efficient VLSI Architecture and Implementation of Power-Optimized Turbo Decoder for LTE Networks." Role of 6G Wireless Networks in AI and Blockchain-Based Applications, edited by Malaya Dutta Borah, et al., IGI Global, 2023, pp. 131-166. https://doi.org/10.4018/978-1-6684-5376-6.ch006

APA

Manjunatha K. N., Raghu N., & Kiran B. (2023). Design of Efficient VLSI Architecture and Implementation of Power-Optimized Turbo Decoder for LTE Networks. In M. Borah, S. Wright, P. Singh, & G. Deka (Eds.), Role of 6G Wireless Networks in AI and Blockchain-Based Applications (pp. 131-166). IGI Global. https://doi.org/10.4018/978-1-6684-5376-6.ch006

Chicago

Manjunatha K. N., Raghu N., and Kiran B. "Design of Efficient VLSI Architecture and Implementation of Power-Optimized Turbo Decoder for LTE Networks." In Role of 6G Wireless Networks in AI and Blockchain-Based Applications, edited by Malaya Dutta Borah, et al., 131-166. Hershey, PA: IGI Global, 2023. https://doi.org/10.4018/978-1-6684-5376-6.ch006

Export Reference

Mendeley
Favorite

Abstract

This chapter explores model, design, and application-specific integrated circuit (ASIC) implementation to optimize turbo decoder using standard cell library of complementary metal oxide semiconductor (CMOS). Various constraints like channel noise, iteration, and frame length performance are analyzed and estimated through reference models. Register transfer language (RTL) model for encoder and decoder are simulated and synthesized by hardware description language (HDL). The ASIC implementation with various performance parameters like power and speed are considered to evaluate the proposed algorithm on decoder blocks. In the proposed low power turbo decoder, novel techniques like clock gating and adaptable iteration methods are used. This work proved the energy efficiency through elimination of unwanted iteration and early stopping mechanism. The results are compared with other competent researches and show that power dissipation is reduced by 34% with adaptable data rates for LTE standard wireless applications.

Request Access

You do not own this content. Please login to recommend this title to your institution's librarian or purchase it from the IGI Global bookstore.