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From MARTE to Reconfigurable NoCs: A Model Driven Design Methodology

From MARTE to Reconfigurable NoCs: A Model Driven Design Methodology

Imran Rafiq Quadri, Majdi Elhaji, Samy Meftali, Jean-Luc Dekeyser
Copyright: © 2010 |Pages: 23
ISBN13: 9781615208074|ISBN10: 1615208070|EISBN13: 9781615208081
DOI: 10.4018/978-1-61520-807-4.ch006
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MLA

Quadri, Imran Rafiq, et al. "From MARTE to Reconfigurable NoCs: A Model Driven Design Methodology." Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication, edited by Jih-Sheng Shen and Pao-Ann Hsiung, IGI Global, 2010, pp. 135-157. https://doi.org/10.4018/978-1-61520-807-4.ch006

APA

Quadri, I. R., Elhaji, M., Meftali, S., & Dekeyser, J. (2010). From MARTE to Reconfigurable NoCs: A Model Driven Design Methodology. In J. Shen & P. Hsiung (Eds.), Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication (pp. 135-157). IGI Global. https://doi.org/10.4018/978-1-61520-807-4.ch006

Chicago

Quadri, Imran Rafiq, et al. "From MARTE to Reconfigurable NoCs: A Model Driven Design Methodology." In Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication, edited by Jih-Sheng Shen and Pao-Ann Hsiung, 135-157. Hershey, PA: IGI Global, 2010. https://doi.org/10.4018/978-1-61520-807-4.ch006

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Abstract

Due to the continuous exponential rise in SoC’s design complexity, there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. We address this issue and propose a novel SoC co-design methodology based on Model Driven Engineering and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by Object Management Group, to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs. In this chapter, we present a high level modeling approach that targets modern Network on Chips systems. The overall objective: to perform system modeling at a high abstraction level expressed in Unified Modeling Language (UML); and afterwards, transform these high level models into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis.

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