FPGA Coprocessor for Simulation of Neural Networks Using Compressed Matrix Storage

FPGA Coprocessor for Simulation of Neural Networks Using Compressed Matrix Storage

Jörg Bornschein
ISBN13: 9781609600181|ISBN10: 1609600185|ISBN13 Softcover: 9781609600198|EISBN13: 9781609600204
DOI: 10.4018/978-1-60960-018-1.ch011
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MLA

Bornschein, Jörg. "FPGA Coprocessor for Simulation of Neural Networks Using Compressed Matrix Storage." System and Circuit Design for Biologically-Inspired Intelligent Learning, edited by Turgay Temel, IGI Global, 2011, pp. 255-275. https://doi.org/10.4018/978-1-60960-018-1.ch011

APA

Bornschein, J. (2011). FPGA Coprocessor for Simulation of Neural Networks Using Compressed Matrix Storage. In T. Temel (Ed.), System and Circuit Design for Biologically-Inspired Intelligent Learning (pp. 255-275). IGI Global. https://doi.org/10.4018/978-1-60960-018-1.ch011

Chicago

Bornschein, Jörg. "FPGA Coprocessor for Simulation of Neural Networks Using Compressed Matrix Storage." In System and Circuit Design for Biologically-Inspired Intelligent Learning, edited by Turgay Temel, 255-275. Hershey, PA: IGI Global, 2011. https://doi.org/10.4018/978-1-60960-018-1.ch011

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Abstract

An FPGA-based coprocessor has been implemented which simulates the dynamics of a large recurrent neural network composed of binary neurons. The design has been used for unsupervised learning of receptive fields. Since the number of neurons to be simulated (>104) exceeds the available FPGA logic capacity for direct implementation, a set of streaming processors has been designed. Given the state- and activity vectors of the neurons at time t and a sparse connectivity matrix, these streaming processors calculate the state- and activity vectors for time t + 1. The operation implemented by the streaming processors can be understood as a generalized form of a sparse matrix vector product (SpMxV). The largest dataset, the sparse connectivity matrix, is stored and processed in a compressed format to better utilize the available memory bandwidth.

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