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System-Level Design of NoC-Based Dependable Embedded Systems

System-Level Design of NoC-Based Dependable Embedded Systems

Mihkel Tagel, Peeter Ellervee, Gert Jervan
Copyright: © 2011 |Pages: 36
ISBN13: 9781609602123|ISBN10: 1609602129|EISBN13: 9781609602147
DOI: 10.4018/978-1-60960-212-3.ch001
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MLA

Tagel, Mihkel, et al. "System-Level Design of NoC-Based Dependable Embedded Systems." Design and Test Technology for Dependable Systems-on-Chip, edited by Raimund Ubar, et al., IGI Global, 2011, pp. 1-36. https://doi.org/10.4018/978-1-60960-212-3.ch001

APA

Tagel, M., Ellervee, P., & Jervan, G. (2011). System-Level Design of NoC-Based Dependable Embedded Systems. In R. Ubar, J. Raik, & H. Vierhaus (Eds.), Design and Test Technology for Dependable Systems-on-Chip (pp. 1-36). IGI Global. https://doi.org/10.4018/978-1-60960-212-3.ch001

Chicago

Tagel, Mihkel, Peeter Ellervee, and Gert Jervan. "System-Level Design of NoC-Based Dependable Embedded Systems." In Design and Test Technology for Dependable Systems-on-Chip, edited by Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, 1-36. Hershey, PA: IGI Global, 2011. https://doi.org/10.4018/978-1-60960-212-3.ch001

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Abstract

Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication problems and to address dependability at various levels of abstraction. This chapter concentrates on system-level design issues of NoC-based systems. It describes various methods proposed for NoC architecture analysis and optimization, and gives an overview of different system-level fault tolerance methods. Finally, the chapter presents a system-level design framework for performing design space exploration for dependable NoC-based systems.

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