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Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis

Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis

Daniel Große, Görschwin Fey, Rolf Drechsler
Copyright: © 2011 |Pages: 13
ISBN13: 9781609602123|ISBN10: 1609602129|EISBN13: 9781609602147
DOI: 10.4018/978-1-60960-212-3.ch005
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MLA

Große, Daniel, et al. "Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis." Design and Test Technology for Dependable Systems-on-Chip, edited by Raimund Ubar, et al., IGI Global, 2011, pp. 119-131. https://doi.org/10.4018/978-1-60960-212-3.ch005

APA

Große, D., Fey, G., & Drechsler, R. (2011). Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. In R. Ubar, J. Raik, & H. Vierhaus (Eds.), Design and Test Technology for Dependable Systems-on-Chip (pp. 119-131). IGI Global. https://doi.org/10.4018/978-1-60960-212-3.ch005

Chicago

Große, Daniel, Görschwin Fey, and Rolf Drechsler. "Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis." In Design and Test Technology for Dependable Systems-on-Chip, edited by Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, 119-131. Hershey, PA: IGI Global, 2011. https://doi.org/10.4018/978-1-60960-212-3.ch005

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Abstract

In this chapter the authors briefly review techniques used in formal hardware verification. An advanced flow emerges from integrating two major methodological improvements: debugging support and coverage analysis. The verification engineer can locate the source of a failure with an automatic debugging support. Components are identified which explain the discrepancy between the property and the circuit behavior. This method is complemented by an approach to analyze functional coverage of the proven Bounded Model Checking (BMC) properties. The approach automatically determines whether the property set is complete or not. In the latter case coverage gaps are returned. Both techniques are integrated in an enhanced verification flow. A running example demonstrates the resulting advantages.

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