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High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis

High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis

Jaan Raik, Urmas Repinski, Maksim Jenihhin, Anton Chepurov
Copyright: © 2011 |Pages: 16
ISBN13: 9781609602123|ISBN10: 1609602129|EISBN13: 9781609602147
DOI: 10.4018/978-1-60960-212-3.ch013
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MLA

Raik, Jaan, et al. "High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis." Design and Test Technology for Dependable Systems-on-Chip, edited by Raimund Ubar, et al., IGI Global, 2011, pp. 294-309. https://doi.org/10.4018/978-1-60960-212-3.ch013

APA

Raik, J., Repinski, U., Jenihhin, M., & Chepurov, A. (2011). High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis. In R. Ubar, J. Raik, & H. Vierhaus (Eds.), Design and Test Technology for Dependable Systems-on-Chip (pp. 294-309). IGI Global. https://doi.org/10.4018/978-1-60960-212-3.ch013

Chicago

Raik, Jaan, et al. "High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis." In Design and Test Technology for Dependable Systems-on-Chip, edited by Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, 294-309. Hershey, PA: IGI Global, 2011. https://doi.org/10.4018/978-1-60960-212-3.ch013

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Abstract

This Chapter addresses the above-mentioned challenges by presenting a holistic diagnosis approach for design error location and malicious fault list generation for soft errors. First, a method for locating design errors at the source-level of hardware description language code using the design representation of high-level decision diagrams is explained. Subsequently, this method is reduced to malicious fault list generation at the high-level. A minimized fault list is generated for optimizing the time to be spent on the fault injection run necessary for assessing designs vulnerability to soft-errors.

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