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Thermal-Aware SoC Test Scheduling

Thermal-Aware SoC Test Scheduling

Zhiyuan He, Zebo Peng, Petru Eles
Copyright: © 2011 |Pages: 21
ISBN13: 9781609602123|ISBN10: 1609602129|EISBN13: 9781609602147
DOI: 10.4018/978-1-60960-212-3.ch019
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MLA

He, Zhiyuan, et al. "Thermal-Aware SoC Test Scheduling." Design and Test Technology for Dependable Systems-on-Chip, edited by Raimund Ubar, et al., IGI Global, 2011, pp. 413-433. https://doi.org/10.4018/978-1-60960-212-3.ch019

APA

He, Z., Peng, Z., & Eles, P. (2011). Thermal-Aware SoC Test Scheduling. In R. Ubar, J. Raik, & H. Vierhaus (Eds.), Design and Test Technology for Dependable Systems-on-Chip (pp. 413-433). IGI Global. https://doi.org/10.4018/978-1-60960-212-3.ch019

Chicago

He, Zhiyuan, Zebo Peng, and Petru Eles. "Thermal-Aware SoC Test Scheduling." In Design and Test Technology for Dependable Systems-on-Chip, edited by Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, 413-433. Hershey, PA: IGI Global, 2011. https://doi.org/10.4018/978-1-60960-212-3.ch019

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Abstract

High temperature has become a technological barrier to the testing of high performance systems-on-chip, especially when deep submicron technologies are employed. In order to reduce test time while keeping the temperature of the cores under test within a safe range, thermal-aware test scheduling techniques are required. In this chapter, the authors address the test time minimization problem as how to generate the shortest test schedule such that the temperature limits of individual cores and the limit on the test-bus bandwidth are satisfied. In order to avoid overheating during the test, the authors partition test sets into shorter test sub-sequences and add cooling periods in between, such that applying a test sub-sequence will not drive the core temperature going beyond the limit. Furthermore, based on the test partitioning scheme, the authors interleave the test sub-sequences from different test sets in such a manner that a cooling period reserved for one core is utilized for the test transportation and application of another core. The authors have proposed an approach to minimize the test application time by exploring alternative test partitioning and interleaving schemes with variable length of test sub-sequences and cooling periods as well as alternative test schedules. Experimental results have shown the efficiency of the proposed approach.

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