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Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels

Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels

Dake Liu, Joar Sohl, Jian Wang
Copyright: © 2012 |Pages: 19
ISBN13: 9781613504567|ISBN10: 161350456X|EISBN13: 9781613504574
DOI: 10.4018/978-1-61350-456-7.ch207
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MLA

Liu, Dake, et al. "Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels." Computer Engineering: Concepts, Methodologies, Tools and Applications, edited by Information Resources Management Association, IGI Global, 2012, pp. 278-296. https://doi.org/10.4018/978-1-61350-456-7.ch207

APA

Liu, D., Sohl, J., & Wang, J. (2012). Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels. In I. Management Association (Ed.), Computer Engineering: Concepts, Methodologies, Tools and Applications (pp. 278-296). IGI Global. https://doi.org/10.4018/978-1-61350-456-7.ch207

Chicago

Liu, Dake, Joar Sohl, and Jian Wang. "Parallel Programming and Its Architectures Based on Data Access Separated Algorithm Kernels." In Computer Engineering: Concepts, Methodologies, Tools and Applications, edited by Information Resources Management Association, 278-296. Hershey, PA: IGI Global, 2012. https://doi.org/10.4018/978-1-61350-456-7.ch207

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Abstract

A novel master-multi-SIMD architecture and its kernel (template) based parallel programming flow is introduced as a parallel signal processing platform. The name of the platform is ePUMA (embedded Parallel DSP processor architecture with Unique Memory Access). The essential technology is to separate data accessing kernels from arithmetic computing kernels so that the run-time cost of data access can be minimized by running it in parallel with algorithm computing. The SIMD memory subsystem architecture based on the proposed flow dramatically improves the total computing performance. The hardware system and programming flow introduced in this article will primarily aim at low-power high-performance embedded parallel computing with low silicon cost for communications and similar real-time signal processing.

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