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Low Complexity Minimal Instruction Set Computer Design using Anubis Cipher for Wireless Identification and Sensing Platform

Low Complexity Minimal Instruction Set Computer Design using Anubis Cipher for Wireless Identification and Sensing Platform

J. H. Kong, L.-M. Ang, K. P. Seng
Copyright: © 2013 |Pages: 28
ISBN13: 9781466619906|ISBN10: 1466619902|EISBN13: 9781466619913
DOI: 10.4018/978-1-4666-1990-6.ch006
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MLA

Kong, J. H., et al. "Low Complexity Minimal Instruction Set Computer Design using Anubis Cipher for Wireless Identification and Sensing Platform." Security and Trends in Wireless Identification and Sensing Platform Tags: Advancements in RFID, edited by Pedro Peris Lopez, et al., IGI Global, 2013, pp. 144-171. https://doi.org/10.4018/978-1-4666-1990-6.ch006

APA

Kong, J. H., Ang, L., & Seng, K. P. (2013). Low Complexity Minimal Instruction Set Computer Design using Anubis Cipher for Wireless Identification and Sensing Platform. In P. Lopez, J. Hernandez-Castro, & T. Li (Eds.), Security and Trends in Wireless Identification and Sensing Platform Tags: Advancements in RFID (pp. 144-171). IGI Global. https://doi.org/10.4018/978-1-4666-1990-6.ch006

Chicago

Kong, J. H., L.-M. Ang, and K. P. Seng. "Low Complexity Minimal Instruction Set Computer Design using Anubis Cipher for Wireless Identification and Sensing Platform." In Security and Trends in Wireless Identification and Sensing Platform Tags: Advancements in RFID, edited by Pedro Peris Lopez, Julio C. Hernandez-Castro, and Tieyan Li, 144-171. Hershey, PA: IGI Global, 2013. https://doi.org/10.4018/978-1-4666-1990-6.ch006

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Abstract

This chapter presents a low complexity processor design for efficient and compact hardware implementation for WISP system security using the involution cipher Anubis algorithm. WISP has scarce resources in terms of hardware and memory, and it is reported that it has 32K of program and 8K of data storage, thus providing sufficient memory for design implementation. The chapter describes Minimal Instruction Set Computer (MISC) processor designs with a flexible architecture and simple hardware components for WISPs. The MISC is able to make use of a small area of the FPGA and provides security programs and features for WISPs. In this chapter, an example application, which is Anubis involution cipher algorithm, is used and proposed to be implemented onto MISC. The proposed MISC hardware architecture for Anubis can be designed and verified using the Handel-C hardware description language and implemented on a Xilinx Spartan-3 FPGA.

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