Reference Hub1
A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC

A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC

K. Tatas, K. Siozios, A. Bartzas, C. Kyriacou, D. Soudris
Copyright: © 2013 |Volume: 4 |Issue: 3 |Pages: 24
ISSN: 1947-9220|EISSN: 1947-9239|EISBN13: 9781466634350|DOI: 10.4018/jaras.2013070101
Cite Article Cite Article

MLA

Tatas, K., et al. "A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC." IJARAS vol.4, no.3 2013: pp.1-24. http://doi.org/10.4018/jaras.2013070101

APA

Tatas, K., Siozios, K., Bartzas, A., Kyriacou, C., & Soudris, D. (2013). A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC. International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), 4(3), 1-24. http://doi.org/10.4018/jaras.2013070101

Chicago

Tatas, K., et al. "A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC," International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) 4, no.3: 1-24. http://doi.org/10.4018/jaras.2013070101

Export Reference

Mendeley
Favorite Full-Issue Download

Abstract

This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach.

Request Access

You do not own this content. Please login to recommend this title to your institution's librarian or purchase it from the IGI Global bookstore.