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SoC Self Test Based on a Test-Processor

SoC Self Test Based on a Test-Processor

Tobial Koal, Rene Kothe, Heinrich Theodor Vierhaus
Copyright: © 2011 |Pages: 17
ISBN13: 9781609602123|ISBN10: 1609602129|EISBN13: 9781609602147
DOI: 10.4018/978-1-60960-212-3.ch016
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MLA

Koal, Tobial, et al. "SoC Self Test Based on a Test-Processor." Design and Test Technology for Dependable Systems-on-Chip, edited by Raimund Ubar, et al., IGI Global, 2011, pp. 360-376. https://doi.org/10.4018/978-1-60960-212-3.ch016

APA

Koal, T., Kothe, R., & Vierhaus, H. T. (2011). SoC Self Test Based on a Test-Processor. In R. Ubar, J. Raik, & H. Vierhaus (Eds.), Design and Test Technology for Dependable Systems-on-Chip (pp. 360-376). IGI Global. https://doi.org/10.4018/978-1-60960-212-3.ch016

Chicago

Koal, Tobial, Rene Kothe, and Heinrich Theodor Vierhaus. "SoC Self Test Based on a Test-Processor." In Design and Test Technology for Dependable Systems-on-Chip, edited by Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, 360-376. Hershey, PA: IGI Global, 2011. https://doi.org/10.4018/978-1-60960-212-3.ch016

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Abstract

Testing complex systems on a chip (SoCs) with up to billions of transistors has been a challenge to IC test technology for more than a decade. Most of the research work in IC test technology has focused on problems of production testing, while the problem of self test in the field of application has found much less attention. With SoCs being used also in long-living systems for safety critical applications, such enhanced self test capabilities become essential for the dependability of the host system. For example, automotive electronic systems must be capable of performing a fast and effective start-up self test. For future self-repairing systems, fault diagnosis will become necessary, since it is the base for dedicated system re-configuration. One way to solve this problem is a hierarchical self-test scheme for embedded SoCs, based on hardware and software. The core of the test architecture then is a test processor device, which is optimised to organize and control test functions efficiently and at minimum cost. This device must be highly reliable by itself. The chapter introduces the basic concept of hierarchical HW / SW based self test, the test processor concept and architecture, and its role in a hierarchical self test scheme for SoCs.

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