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Design for Testability of High-Speed Advance Multipliers: Design for Testability

Design for Testability of High-Speed Advance Multipliers: Design for Testability

Suman Lata Tripathi
Copyright: © 2020 |Pages: 16
ISBN13: 9781799814641|ISBN10: 1799814645|ISBN13 Softcover: 9781799814658|EISBN13: 9781799814665
DOI: 10.4018/978-1-7998-1464-1.ch010
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MLA

Tripathi, Suman Lata. "Design for Testability of High-Speed Advance Multipliers: Design for Testability." AI Techniques for Reliability Prediction for Electronic Components, edited by Cherry Bhargava, IGI Global, 2020, pp. 175-190. https://doi.org/10.4018/978-1-7998-1464-1.ch010

APA

Tripathi, S. L. (2020). Design for Testability of High-Speed Advance Multipliers: Design for Testability. In C. Bhargava (Ed.), AI Techniques for Reliability Prediction for Electronic Components (pp. 175-190). IGI Global. https://doi.org/10.4018/978-1-7998-1464-1.ch010

Chicago

Tripathi, Suman Lata. "Design for Testability of High-Speed Advance Multipliers: Design for Testability." In AI Techniques for Reliability Prediction for Electronic Components, edited by Cherry Bhargava, 175-190. Hershey, PA: IGI Global, 2020. https://doi.org/10.4018/978-1-7998-1464-1.ch010

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Abstract

An efficient design for testability (DFT) has been a major thrust of area for today's VLSI engineers. A poorly designed DFT would result in losses for manufacturers with a considerable rework for the designers. BIST (built-in self-test), one of the promising DFT techniques, is rapidly modifying with the advances in technology as the device shrinks. The increasing complexities of the hardware have shifted the trend to include BISTs in high performance circuitry for offline as well as online testing. Work done here involves testing a circuit under test (CUT) with built in response analyser and vector generator with a monitor to control all the activities.

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