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CNTFET-Based Ternary Logic Gates: Design and Analysis Approach

CNTFET-Based Ternary Logic Gates: Design and Analysis Approach

Suman Rani, Balwinder Singh
Copyright: © 2020 |Pages: 21
ISBN13: 9781799813934|ISBN10: 1799813932|ISBN13 Softcover: 9781799813941|EISBN13: 9781799813958
DOI: 10.4018/978-1-7998-1393-4.ch005
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MLA

Rani, Suman, and Balwinder Singh. "CNTFET-Based Ternary Logic Gates: Design and Analysis Approach." Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET), edited by Balwinder Raj, et al., IGI Global, 2020, pp. 72-92. https://doi.org/10.4018/978-1-7998-1393-4.ch005

APA

Rani, S. & Singh, B. (2020). CNTFET-Based Ternary Logic Gates: Design and Analysis Approach. In B. Raj, M. Khosla, & A. Singh (Eds.), Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET) (pp. 72-92). IGI Global. https://doi.org/10.4018/978-1-7998-1393-4.ch005

Chicago

Rani, Suman, and Balwinder Singh. "CNTFET-Based Ternary Logic Gates: Design and Analysis Approach." In Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET), edited by Balwinder Raj, Mamta Khosla, and Amandeep Singh, 72-92. Hershey, PA: IGI Global, 2020. https://doi.org/10.4018/978-1-7998-1393-4.ch005

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Abstract

In the recent digital designs, there are certain circumstances where energy efficiency and ease is required, and in such situations, ternary logic (or three-valued logic) is favored. Ternary logic is an auspicious supernumerary to the conventional binary (0, 1) logic design techniques as this one is possible to attain straightforwardness and energy efficiency. This chapter deals with the comparative analysis of CMOS and CNTFET-based ternary inverter and universal gates design. The simulation result is analyzed and validated with a Hailey simulation program with integrated circuit (HSPICE) simulations. The average delay and power consumption in CNTFET-based ternary inverter have been reduced by approximately 90.3% and 48.8% respectively, as compared to CMOS-based ternary inverter design. Likewise, delay is reduced by 50% and power gets 99% reduction in ternary CNTFET NAND gate as compared to CMOS-based ternary NAND gat. It is concluded that CNFETs are faster and consume less power compared to CMOS technology.

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