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Performance Analysis of FPGA Architectures based Embedded Control Applications

Performance Analysis of FPGA Architectures based Embedded Control Applications

Slim Ben Othman, Ahmed Karim Ben Salem, Slim Ben Saoud
Copyright: © 2011 |Pages: 37
ISBN13: 9781609600860|ISBN10: 160960086X|EISBN13: 9781609600884
DOI: 10.4018/978-1-60960-086-0.ch011
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MLA

Ben Othman, Slim, et al. "Performance Analysis of FPGA Architectures based Embedded Control Applications." Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, edited by Mohamed Khalgui and Hans-Michael Hanisch, IGI Global, 2011, pp. 274-310. https://doi.org/10.4018/978-1-60960-086-0.ch011

APA

Ben Othman, S., Ben Salem, A. K., & Ben Saoud, S. (2011). Performance Analysis of FPGA Architectures based Embedded Control Applications. In M. Khalgui & H. Hanisch (Eds.), Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility (pp. 274-310). IGI Global. https://doi.org/10.4018/978-1-60960-086-0.ch011

Chicago

Ben Othman, Slim, Ahmed Karim Ben Salem, and Slim Ben Saoud. "Performance Analysis of FPGA Architectures based Embedded Control Applications." In Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, edited by Mohamed Khalgui and Hans-Michael Hanisch, 274-310. Hershey, PA: IGI Global, 2011. https://doi.org/10.4018/978-1-60960-086-0.ch011

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Abstract

The performances of System on Chip (SoC) and the Field Programmable Gate Array (FPGA) particularly, are increasing continually. Due to the growing complexity of modern embedded control systems, the need of more performance digital devices is evident. Recent FPGA technology makes it possible to include processor cores into the FPGA chip, which ensures more flexibility for digital controllers. Indeed, greater functionality of hardware and system software, Real-Time (RT) platforms and distributed subsystems are demanded. In this chapter, a design concept of FPGA based controller with Hardware/Software (Hw/Sw) codesign is proposed. It is applied for electrical machine drives. There are discussed different MultiProcessor SoC (MPSoC) architectures with Hw peripherals for the implementation on FPGA-based embedded processor cores. Hw accelerators are considered in the design to enhance the controller speed performance and reduce power consumption. Test and validation of this control system are performed on a RT motor emulator implemented on the same FPGA. Experimental results, carried on a real prototyping platform, are given in order to analyze the performance and efficiency of discussed architecture designs helping to support hard RT constraints.

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