Performance Analysis of FPGA Architectures based Embedded Control Applications

Performance Analysis of FPGA Architectures based Embedded Control Applications

Slim Ben Othman (National Institute of Applied Sciences and Technology (INSAT), Tunisia), Ahmed Karim Ben Salem (National Institute of Applied Sciences and Technology (INSAT), Tunisia) and Slim Ben Saoud (National Institute of Applied Sciences and Technology (INSAT), Tunisia)
DOI: 10.4018/978-1-60960-086-0.ch011
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Abstract

The performances of System on Chip (SoC) and the Field Programmable Gate Array (FPGA) particularly, are increasing continually. Due to the growing complexity of modern embedded control systems, the need of more performance digital devices is evident. Recent FPGA technology makes it possible to include processor cores into the FPGA chip, which ensures more flexibility for digital controllers. Indeed, greater functionality of hardware and system software, Real-Time (RT) platforms and distributed subsystems are demanded. In this chapter, a design concept of FPGA based controller with Hardware/Software (Hw/Sw) codesign is proposed. It is applied for electrical machine drives. There are discussed different MultiProcessor SoC (MPSoC) architectures with Hw peripherals for the implementation on FPGA-based embedded processor cores. Hw accelerators are considered in the design to enhance the controller speed performance and reduce power consumption. Test and validation of this control system are performed on a RT motor emulator implemented on the same FPGA. Experimental results, carried on a real prototyping platform, are given in order to analyze the performance and efficiency of discussed architecture designs helping to support hard RT constraints.
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Introduction

Nowadays, digital controllers are widely used in different industrial application areas such as motion control, power electronics, and motor control. Efficiency of control device technologies has been proven with the use of highly optimized DSP controllers. However, System on Chip (SoC) capability introduces new challenges in the design process. Codesign becomes a crucial issue where software and hardware must be developed together and different design and modeling techniques have been used.

In the last years, several research studies proved that Field Programmable Gate Array (FPGA), are an appropriate alternative to implement digital controllers in several application areas, such as motion control, power electronics, and motor control over pure software solutions (DSP, Microcontrollers) and analog solutions (Rodriguez-Andina, Moure, & Valdes, 2007; Yuen Fong, Moallem, & Wei, 2007). FPGA-based controllers offer advantages such as high speed, complex functionality, and low power consumption. Even, FPGA-based computing platforms, with embedded processors, have been more potential to implement extreme high-performance applications without the up-front risk of creating custom fixed function hardware (Seul & Sung su, 2007). One of the often-overlooked benefits of using embedded processors within FPGA is the ability to create a Hardware/Software (Hw/Sw) development target within a single programmable device. Different approaches were used to obtain more speed performance like the use of embedded MultiProcessor SoC (MPSoC) (Kumar, Fernando, Yajun, Mesman, & Corporaal, 2007) or specific Hw coprocessor accelerator (Pellerin & Shenoy, 2006).

Embedded control system designs are often complicated by strict performance, area, and power constraints (Carlos Paiz & Porrmann, 2007). The rigidity of the target architecture may lead to a very restricted application field or poor performances (Zergainoh, Baghdadi, & Jerraya, 2004). The MPSoC remains a promising architecture to ensure a correct behavior of the embedded closed loop controller. Nevertheless, one of the most important issues in MPSoC design is the target architecture. In this chapter, different FPGA-based MPSoC architectures are proposed. The authors discuss the Hw/Sw flow design according to the InterProcessor Communication (IPC) supports, and analyze the impact of architecture models on embedded system performances.

However, modularity, flexibility and scalability are required to have an efficient application specific multiprocessor design flow (Carlos Paiz & Porrmann, 2007). This has led to the study of Hw/Sw codesign issues. These issues traditionally arise from applications where there are fixed constraints that cannot be met in software but do not warrant a fully Hw solution.

Considering the programmable logic inside the FPGA as an extension to the embedded processor, processing tasks of the application can be distributed conveniently and efficiently between hardware and software. This chapter also discusses the design of an application-specific MPSoC, including generation of Hw/Sw wrappers that adapts the processors to the on-chip control system applications and results to a great deal of performance.

As well, the rapid development of the fully embedded control system is pending on not only the SoC target knowledge and equipment needed to fabricate any prototype but also on the accurate modeling and simulation of the digital closed-loop controller in its power and analog context. It requires extensive testing before applying in real conditions.

The proposed wok, aims to define a new FPGA-based design flow that instantly allows validation and prototyping of the digital Controller Under Test (CUT). The proposed approach leads to an embedded simulation approach composed by the CUT and the Real Time (RT) process emulator implemented in the same SoC. Therefore, the implementation concept, will be used either for complete controller device validation at the designing and validation stage or for diagnosis at normal functioning stage.

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