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Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip

Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip

Parisa Khadem Hamedani, Natalie Enright Jerger, Shaahin Hessabi, Hamid Sarbazi-Azad
Copyright: © 2013 |Volume: 4 |Issue: 3 |Pages: 19
ISSN: 1947-9220|EISSN: 1947-9239|EISBN13: 9781466634350|DOI: 10.4018/jaras.2013070103
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MLA

Hamedani, Parisa Khadem, et al. "Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip." IJARAS vol.4, no.3 2013: pp.42-60. http://doi.org/10.4018/jaras.2013070103

APA

Hamedani, P. K., Jerger, N. E., Hessabi, S., & Sarbazi-Azad, H. (2013). Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip. International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), 4(3), 42-60. http://doi.org/10.4018/jaras.2013070103

Chicago

Hamedani, Parisa Khadem, et al. "Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip," International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) 4, no.3: 42-60. http://doi.org/10.4018/jaras.2013070103

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Abstract

This paper proposes three ILP-based static thermal-aware mapping algorithms for 3D Networks-on-Chip (NoC). With these three mapping algorithms, the authors explore the thermal constraints and their effects on temperature and performance. Through complexity analysis, the authors show that the first algorithm, an optimal one, is not suitable for 3D NoCs. Therefore, the authors develop two approximation algorithms and analyze their algorithmic complexities to show their proficiency. According to simulation results, mapping algorithms that employ direct thermal calculation to minimize the temperature reduce the peak temperature by up to 24% and 22%, for the benchmarks that have the highest communication rate and largest number of tasks, respectively. This peak temperature reduction comes at the price of a higher power-delay product. The authors’ exploration shows that considering power balancing early in the mapping algorithm does not affect chip temperature. Moreover, the authors show that considering explicit performance constraints in the thermal mapping has no major effect on performance.

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