An FPGA-Based Reconfigurable FIR Filter for SDR Applications

An FPGA-Based Reconfigurable FIR Filter for SDR Applications

Lincoln Alexandre Paz Silva, Francisco de Assis Brito-Filho
Copyright: © 2022 |Pages: 8
DOI: 10.4018/IJITN.326455
OnDemand:
(Individual Articles)
Available
$37.50
Current Special Offers
No Current Special Offers
TOTAL SAVINGS: $37.50

Abstract

This article presents a proposal of a reconfigurable FIR filter capable of covering the most common wireless communication standards on software-defined radio applications. The filter was implemented using a low-cost field programmable gate array, Cyclone IV EP4CE22F17C6 model from Altera®. System design is presented together with simulation results. Validation is done for a 500 kHz base-band noisy signal. The synthesized design uses 5,259 logic elements of which 4,778 were used for combinational logic blocks and 513 for dedicated logic registers, which represents 22% of total used FPGA capacity. The maximum sampling frequency supported by the architecture is 23.24 MHz.

Complete Article List

Search this Journal:
Reset
Volume 16: 1 Issue (2024)
Volume 15: 1 Issue (2023)
Volume 14: 1 Issue (2022)
Volume 13: 4 Issues (2021)
Volume 12: 4 Issues (2020)
Volume 11: 4 Issues (2019)
Volume 10: 4 Issues (2018)
Volume 9: 4 Issues (2017)
Volume 8: 4 Issues (2016)
Volume 7: 4 Issues (2015)
Volume 6: 4 Issues (2014)
Volume 5: 4 Issues (2013)
Volume 4: 4 Issues (2012)
Volume 3: 4 Issues (2011)
Volume 2: 4 Issues (2010)
Volume 1: 4 Issues (2009)
View Complete Journal Contents Listing