The Hamming weight of a codeword is the number of 1’s of the codeword. The Hamming distance between any two codewords is the number of bits with which the words differ from each other, and the minimum distance of a code is the smallest Hamming distance between two code words. The larger the distance the better the performance of a code. Very long and large girth LDPC codes tend to have larger minimum distances. Minimum distance can be used as a measure to rank these codes.
Published in Chapter:
Development of an Efficient and Secure Mobile Communication System with New Future Directions
Abid Yahya (Universiti Malaysia Perlis, Malaysia), Farid Ghani (Universiti Malaysia Perlis, Malaysia), R. Badlishah Ahmad (Universiti Malaysia Perlis, Malaysia), Mostafijur Rahman (Universiti Malaysia Perlis, Malaysia), Aini Syuhada (Universiti Malaysia Perlis, Malaysia), Othman Sidek (Collaborative Microelectronic Design Excellence Center, Malaysia), and M. F. M. Salleh (Universiti Sains Malaysia, Malaysia)
Copyright: © 2012
|Pages: 20
DOI: 10.4018/978-1-61350-116-0.ch010
Abstract
This chapter presents performance of a new technique for constructing Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) encrypted codes based on a row division method. The new QC-LDPC encrypted codes are flexible in terms of large girth, multiple code rates, and large block lengths. In the proposed algorithm, the restructuring of the interconnections is developed by splitting the rows into subrows. This row division reduces the load on the processing node and ultimately reduces the hardware complexity. In this method of encrypted code construction, rows are used to form a distance graph. They are then transformed to a parity-check matrix in order to acquire the desired girth. In this work, matrices are divided into small sub-matrices, which result in improved decoding performance and reduce waiting time of the messages to be updated. Matrix sub-division increases the number of sub-matrices to be managed and memory requirement. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip.