Recent focus has been placed on exploring the possibility to switch from parallel to serial data links between NoC routers in order to improve signal integrity in the communication channel. However... Show More

Recent focus has been placed on exploring the possibility to switch from parallel to serial data links between NoC routers in order to improve signal integrity in the communication channel. However, moving streams of data between the parallel path of the internal router and external serial-channel links between them consumes additional power. One challenge is encoding the data and minimise the switching activity of data in the serial links in order to reduce the additional power dissipation; while under real-time and minimal hardware constraints. Consequently, proposed is a novel low area/power decision circuit for NoC channel encoding which identifies in real-time packets for encoding and extends the existing SILENT encoders/decoders to further minimise power consumption and demonstrates the power performance savings of the decision circuit and modified (en)decoders using example test traffic with the EMBRACE NoC router, a mixed signal spiking neural network (SNNs) embedded platform.

The evolvable hardware (EHW) paradigm facilitates the construction of autonomous systems that can adapt to environmental changes and degradation of the computational resources. Extending the EHW... Show More

The evolvable hardware (EHW) paradigm facilitates the construction of autonomous systems that can adapt to environmental changes and degradation of the computational resources. Extending the EHW principle to architectural adaptation, the authors study the capability of evolvable hardware classifiers to adapt to intentional run-time fluctuations in the available resources, i.e., chip area, in this work. To that end, the authors leverage the Functional Unit Row (FUR) architecture, a coarse-grained reconfigurable classifier, and apply it to two medical benchmarks, the Pima and Thyroid data sets from the UCI Machine Learning Repository. While quick recovery from architectural changes was already demonstrated for the FUR architecture, the authors also introduce two reconfiguration schemes helping to reduce the magnitude of degradation after architectural reconfiguration.

Transport triggered architectures are used for implementing bio-inspired systems due to their simplicity, modularity and fault-tolerance. However, producing efficient, optimised machine code for... Show More

Transport triggered architectures are used for implementing bio-inspired systems due to their simplicity, modularity and fault-tolerance. However, producing efficient, optimised machine code for such architectures is extremely difficult, since computational complexity has moved from the hardware-level to the software-level. Presented is the application of Cartesian Genetic Programming (CGP) to the evolution of machine code for a simple implementation of transport triggered architecture. The effectiveness of the algorithm is demonstrated by evolving machine code for a 4-bit multiplier with three different levels of parallelism. The results show that 100% successful solutions were found by CGP and by further optimising the size of the solutions, it’s possible to find efficient implementations of the 4-bit multiplier. Further analysis of the solutions showed that use of loops within the CGP function set could be beneficial and was demonstrated by repeating the earlier 4-bit multiplier experiment with the addition of a loop function.

The authors formulate the body pose estimation as a multi-dimensional nonlinear optimization problem, suitable to be approximately solved by a meta-heuristic, specifically, the particle swarm... Show More

The authors formulate the body pose estimation as a multi-dimensional nonlinear optimization problem, suitable to be approximately solved by a meta-heuristic, specifically, the particle swarm optimization (PSO). Starting from multi-view video sequences acquired in a studio environment, a full skeletal configuration of the human body is retrieved. They use a generic subdivision-surface body model in 3-D to generate solutions for the optimization problem. PSO then looks for the best match between the silhouettes generated by the projection of the model in a candidate pose and the silhouettes extracted from the original video sequence. The optimization method, in this case PSO, is run in parallel on the Graphics Processing Unit (GPU) and is implemented in Cuda-C™ on the nVidia CUDA™ architecture. The authors compare the results obtained by different configurations of the camera setup, fitness function, and PSO neighborhood topologies.