This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a... Show More

This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach.

Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, the authors present an efficient and reliable... Show More

Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, the authors present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5×6 crossbar is used for the proposed architecture which requires one more 5×1 multiplexer without increasing the critical path delay of the router as compared to the 5×5 crossbar. The proposed router has been simulated for uniform, transpose and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead.

This paper proposes three ILP-based static thermal-aware mapping algorithms for 3D Networks-on-Chip (NoC). With these three mapping algorithms, the authors explore the thermal constraints and their... Show More

This paper proposes three ILP-based static thermal-aware mapping algorithms for 3D Networks-on-Chip (NoC). With these three mapping algorithms, the authors explore the thermal constraints and their effects on temperature and performance. Through complexity analysis, the authors show that the first algorithm, an optimal one, is not suitable for 3D NoCs. Therefore, the authors develop two approximation algorithms and analyze their algorithmic complexities to show their proficiency. According to simulation results, mapping algorithms that employ direct thermal calculation to minimize the temperature reduce the peak temperature by up to 24% and 22%, for the benchmarks that have the highest communication rate and largest number of tasks, respectively. This peak temperature reduction comes at the price of a higher power-delay product. The authors’ exploration shows that considering power balancing early in the mapping algorithm does not affect chip temperature. Moreover, the authors show that considering explicit performance constraints in the thermal mapping has no major effect on performance.

Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which... Show More

Technology scaling has brought about dramatic rises in the on-chip power density of modern microprocessors. This has led to greater scrutiny and awareness of thermal management techniques which allows to uphold the thermal integrity of the chip. Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future thermal problems would include 3D circuits. Three-dimensional technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology also exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. This paper presents an exploration of temperature-aware placement approaches in both the 2D and 3D stacked systems. Various thermal models were developed to investigate the effect of uniform power distribution, thermal-aware placement in 2D chips and 3D stacked systems on the thermal performance of the system thereby providing with metrics which can be used for thermal-aware mapping.

Architectures for Wireless Sensor Networks platforms have not evolved as expected during the past decade. The monolithic principles of the first nodes are still followed in the new designs. The... Show More

Architectures for Wireless Sensor Networks platforms have not evolved as expected during the past decade. The monolithic principles of the first nodes are still followed in the new designs. The architectures are not prepared to include upgrades such as new energy management modules or even more energy efficient communication units. This leads to constraints on the development of new protocols and applications, since the software takes the entire burden on the reconfigurability and optimization that could be done by a modular architecture. In this work, the authors propose a new platform - MoteIST - with a different architecture, introducing higher modularity and addressing the energy management issues, while maintaining the compatibility with previously designed software and sensing boards. The authors’ design enables different energy management solutions, including harvesting modules and different communication units, such as wake-up, sub-1 GHz and 2.4 GHz radios. The authors describe the implementation and analyze the relevant characteristics of MoteIST, namely its memory footprint and power profile.

Small embedded systems operating in unattended conditions do need to be perpetually powered if a truly pervasive paradigm is envisaged. Harvesting energy from the surrounding environment seems to be... Show More

Small embedded systems operating in unattended conditions do need to be perpetually powered if a truly pervasive paradigm is envisaged. Harvesting energy from the surrounding environment seems to be the best option. For that, a set of systems has been proposed featuring interesting solutions but not yet capable of overcoming some issues like performance and flexibility. The authors propose a novel design for an environmental energy harvesting power supply that not only can work with multiple energy sources but also can extract the maximum possible energy from them. Additionally, it can provide important information concerning the energy resources of the system. Focusing particularly on the system’s design, the authors present results from a reference implementation that highlight the low wasted power and high efficiency characteristics of the system.