Low Power Design Techniques: Classical and beyond CMOS Era

Low Power Design Techniques: Classical and beyond CMOS Era

Mohd Samar Ansari (Aligarh Muslim University, India) and Shailendra Kumar Tripathi (Malaviya National Institute of Technology, India)
Copyright: © 2016 |Pages: 26
DOI: 10.4018/978-1-5225-0190-9.ch001
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Abstract

Conventional CMOS based IC implementations are soon expected to attain a state of saturation mainly due to technological barriers and physical constraints. A number of nanoelectronic devices that may be viable alternatives to standard CMOS have been put forward, and these could pave way for even lower power circuits. Some worthy contenders are carbon nanotube field effect transistor, nanowire field effect transistor, tunnel field effect transistor, and the single electron transistor. In this chapter, device- and circuit-level techniques have been discussed for designing low power circuits in conventional CMOS. Moreover, various sources of power consumption have been reviewed. It is also attempted to review the major components of power i.e. dynamic, short-circuit, and leakage, followed by basics of device and circuit level techniques to reduce the power components. Further, pertinent features of emerging nanoelectronic devices are discussed. These beyond-CMOS devices are expected to revolutionize the era of electronic systems with their low power & high performance characteristics.
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1. Introduction

The major concerns of VLSI designers in 90’s era were high speed, small area and low cost, but the issue of power somehow got less importance. However, since the past decade, the expansion of personal computing devices and wireless communication systems has forced designers to investigate low power techniques with high reliability. The portable and handheld products would exhibit lower battery life with difficulties in heat exhausting without the use of low-power design methodologies (Roy, 2009). Moreover, reliability is strongly affected by power consumption. In addition to this, high power dissipation implies high temperature operation, which could result in number of failures in the system. It could be said that, the lower the power dissipation of a product, the lesser electricity that is consumed and the lower the impact on global environment. Moreover, utilizing low-power components in combination with low-power design techniques is desirable in the present time. Therefore, the requirements for low power consumption go on increasing drastically with the need of battery-powered multifunctional portable devices (Roy, 2009; Chandrakasan, 2012; Rabaey, 2012).

The motivations for reducing power consumption are application specific. Such as, for mobile phones, the objective is to maintain long battery lifetime and light weight with reasonable and low cost packaging. In the case of portable computers such as laptops, the goal is to decrease the power requirement of the electronics portion of the system to a point which is approximately half of the whole power consumption (Rabaey, 2009). Additionally, for high performance systems operated without battery such as workstations, the target of power minimization is to cut the system price while ensuring device reliability. These factors have motivated low power techniques for CMOS technology. Moreover, with technology scaling and increasing performance necessities, the power levels to the chip are rising with reduced supply voltages. This also puts a heavy demand on the battery technology which serves the actual circuit.

There are numerous techniques that have been introduced over the previous decade to tackle power reduction needs of the high performance circuits and systems. The fundamental low-power design methodologies, such as clock gating for decreasing dynamic power, or multiple voltage thresholds to reduce leakage current, are well-recognized and supported by existing tools (Horowitz, 2005; Thompson, 2006).

From the past several years, it is seen that the continued scaling in the device size of CMOS transistor leads to an increased risk of considerable power consumption, low yield, and reliability degradation in integrated circuits (Kuhn, 2012). The power consumption has turned into a critical issue in present time because of global warming. That leads to the requirement of low power circuits or even self-sustainable devices to meet the expectations of modern trends. In recent times, it is accepted that these limitations of the Si-MOSFET device require the semiconductor industry to investigate new materials and devices which are able to complement the CMOS transistor before silicon based technology reaches its limits towards the end of present decade, with the channel length of MOS approaching values under 10 nm (Skotnicki, 2005; Borkar, 2006; Marković, 2010). New ways and means to extend the saturating Moore’s law are therefore needed.

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