Statistical Simulations on Perceptron-Based Adders

Statistical Simulations on Perceptron-Based Adders

Snorre Aunet (University of Oslo, Norway & Centers for Neural Inspired Nano Architectures, Norway) and Hans Kristian Otnes Berge (University of Oslo, Norway)
Copyright: © 2009 |Pages: 8
DOI: 10.4018/978-1-59904-849-9.ch216
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Abstract

In this article we compare a number of full-adder (1- bit addition) cells regarding minimum supply voltage and yield, when taking statistical simulations into account. According to the ITRS Roadmap two of the most important challenges for future nanoelectronics design are reducing power consumption and increasing manufacturability (ITRS, 2005). We use subthreshold CMOS, which is regarded by many as the most promising ultra low power circuit technique. It is also shown that a minimum redundancyfactor as low as 2 is sufficient to make circuits maintain full functionality under the presence of defects. This is, to our knowledge, the lowest redundancy reported for comparable circuits, and builds on a method suggested a few years ago (Aunet & Hartmann, 2003). A standard Full-Adder (FA) and an FA based on perceptrons exploiting the “mirrored gate”, implemented in a standard 90 nm CMOS technology, are shown not to withstand statistical mismatch and process variations for supply voltages below 150 mV. Exploiting a redundancy scheme tolerating “open” faults, with gate-level redundancy and shorted outputs, shows that the same two FAs might produce adequate Sum and Carry outputs at the presence of a defect PMOS for supply voltages above 150 mV, for a redundancy factor of 2 (Aunet & Otnes Berge, 2007). Two additional perceptrons do not tolerate the process variations, according to simulations. Simulations suggest that the standard FA has the lowest power consumption. Power consumption varies more than an order of magnitude for all subthreshold FAs, due to the statistical variations
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Background

The first simple mathematical model of the biological neurons, published by McCulloch and Pitts in 1943, calculates the sign of the weigthed sum of inputs. Sometimes such circuits are called threshold logic gates or threshold elements. Perceptrons may be used to implement Neural Networks as well as digital signal processing.

Nanoscale CMOS technology is expected to be used alongside other technologies in the future. A typical chip will fail if even a single transistor or wire on the chip is defective. Reducing the power consumption and making defect tolerant circuits have been pointed out as important issues (Mead, 1990), (ITRS, 2005).

Reducing the power supply voltage is the most direct and dramatic means of reducing the power consumption (Liu & Svensson, 1993), and subthreshold circuits operating with a supply voltage, Vdd, less than the absolute value of the inherent threshold voltages, Vt, has been known for decades (Swensson, Meindl, 1972).

For older technologies, where manufacturability including threshold voltage variability, was not such an important issue (ITRS 2005),(Wong, Mittal, Cao & Starr, 2004) the minimum supply voltages have often been estimated without mismatch and process variations being taken into account (Liu & Svensson, 1993),(Schrom & Selberherr, 1996). To get more realistic estimates we have simulated and compared 4 different topologies for 1-bit addition under statistical variations in the process and matching properties.

Key Terms in this Chapter

Mismatch: Ideally identically constructed elements on an integrated circuits have a mismatch when they differ in their physical properties after production of the chip.

Parameter Variations: Parameters describing physical traits of integrated circuits may have variations due to mismatch, for example the threshold voltages of transistors.

Full Adder: Circuit that produces the binary sum and carry when adding two binary numbers.

Nanoscale CMOS: CMOS technologies where dimensions smaller than 100 nm is critical to the functioning of the produced chip.

Monte Carlo Simulations: Computer simulations basing the results on statistical distribution of parameters.

Yield: In this paper the term yield refers to the ratio of functional circuits to the total number of simulated circuits. Often yield refers to the ratio of functional chips to the total number of manufactured chips.

Perceptron: Type of artificial (feedforward) Neural Network.§

Minority-3 Gate: A minority 3 gate outputs a logic “0” signal if, and only if, 2 or 3 out of it’s three binary inputs are “1”.

Neuron: Electrically excitable cells in the nervous system that process and transmit information.

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