Power emulation extends the hardware emulation technique with power sensors and corresponding power models in order to gather estimated power analysis data of the design-under-test.
Published in Chapter:
Industrial Applications of Emulation Techniques for the Early Evaluation of Secure Low-Power Embedded Systems
Norbert Druml (Graz University of Technology, Austria), Manuel Menghin (Graz University of Technology, Austria), Christian Steger (Graz University of Technology, Austria), Armin Krieg (Infineon Technologies Austria, Austria), Andreas Genser (Infineon Technologies Austria, Austria), Josef Haid (Infineon Technologies Austria, Austria), Holger Bock (Infineon Technologies Austria, Austria), and Johannes Grinschgl (Independent Researcher, Austria)
Copyright: © 2014
|Pages: 19
DOI: 10.4018/978-1-4666-6194-3.ch013
Abstract
Embedded systems that follow a secure and low-power design methodology are, besides keeping strict design constraints, heavily dependent on comprehensive test and verification procedures. The large set of possible test vectors and the increasing density of System-on-Chip designs call for the introduction of hardware-accelerated techniques to solve the verification time problem. As already described earlier, emulation-based methodologies based on FPGA evaluation platforms prove capable of providing a solution compared to traditional system simulation. This chapter gives an introduction into a multi-disciplinary emulation-based design evaluation and verification methodology that is based on various techniques that have been presented in chapter 5. Test and verification capabilities are enhanced by the augmentation of this approach using model-based analysis units: gate-level-based power consumption models, power supply network models, event-based performance monitors, and high-level fault modes. The feasible usage of this verification methodology in the field of contactlessly powered smart cards is finally demonstrated using several industrial case studies.