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TopOn-chip power consumption in memories becomes a challenge with the use of deep submicron technologies. Alipour et al. (2011) explores a design space for memory architecture. This helps chip designers find cache sizes for optimum power consumption and performance for embedded processors.
Set-associative caches are used to improve cache hit rate but have higher energy consumption than direct-mapped cache due to some wasted energy dissipation (Powel et al., 2001) since, regardless of the number of banks in a set, only one bank has the desired data for a cache hit.
To resolve the energy issue, Hasegawa et al. (1995) proposed a low-power set-associative cache scheme, now commonly referred to as phased cache. In phased cache, all the tags are accessed in the first phase, and if one tag matches to a reference address, only one data block in a bank is accessed as the second phase. The basic idea is to avoid unnecessary data access to reduce power consumption. The disadvantage of a phased cache is a poor performance caused by using more clock cycles to access desired data, compared to other conventional caches.
Taking advantage of power savings over phased cache, Inoue et al. (1999) proposed a low-power set-associative cache scheme, called way-prediction cache that improves the latency of phased cache. The MRU (most recently used) algorithm is popular to predict one of the n banks to access. If the prediction is correct, the tag and data block are accessed in one cycle with the speed and power savings like direct-mapped cache. If the prediction is wrong, the rest of the banks are accessed during the next cycle in parallel. The performance and power efficiency of way-prediction cache is highly dependent on the accuracy of a way-prediction algorithm used.
Chung et al. (2008) proposes a pipeline change for way determination. An early tag lookup stage, between branch prediction and fetch stage, is used to determine the next way to be accessed. In this method, prediction accuracy and hit rate of the original way-prediction cache are maintained while reducing power consumption. Chung et al. (2008) did not evaluate this scheme for data caches since the early tag lookup stage was proposed for instruction cache only.