Article Preview
TopPrevious Work
A number of NoC architectures have been implemented and evaluated in both FPGA and ASIC platforms, among them (Ehliar & Liu, 2007; Genko, Atienza, & De Micheli, 2005). Furthermore, frameworks and tools for high-level exploration for NoC architectures exist (Kumar, Hansson, Huisken, & Corporaal, 2007).
In Leary and Chatha (2010) a holistic algorithm for NoC synthesis able to address all these requirements together in an integrated manner was presented. However, the synthesis methodology provided does not provide Register Transfer-Level descriptions that can readily be used for system implementation.
In Strano, A., Bertozzi, D., Angiolini, F., Di Gregorio, L., Sem-Jacobsen, F. O., Todorov, V., Flich, J., Silla, F., & Bjerregaard, T. (2012) a more complete framework for the design of NoC is presented, but it does not include FPGA rapid prototyping.