Automatic Machine Code Generation for a Transport Triggered Architecture using Cartesian Genetic Programming

Automatic Machine Code Generation for a Transport Triggered Architecture using Cartesian Genetic Programming

James Alfred Walker (Department of Electronics, University of York, York, UK), Yang Liu (Department of Electronics, University of York, York, UK), Gianluca Tempesti (Department of Electronics, University of York, York, UK), Jon Timmis (Departments of Electronics and Computer Science, University of York, York, UK) and Andy M. Tyrrell (Department of Electronics, University of York, York, UK)
DOI: 10.4018/jaras.2012100103

Abstract

Transport triggered architectures are used for implementing bio-inspired systems due to their simplicity, modularity and fault-tolerance. However, producing efficient, optimised machine code for such architectures is extremely difficult, since computational complexity has moved from the hardware-level to the software-level. Presented is the application of Cartesian Genetic Programming (CGP) to the evolution of machine code for a simple implementation of transport triggered architecture. The effectiveness of the algorithm is demonstrated by evolving machine code for a 4-bit multiplier with three different levels of parallelism. The results show that 100% successful solutions were found by CGP and by further optimising the size of the solutions, it’s possible to find efficient implementations of the 4-bit multiplier. Further analysis of the solutions showed that use of loops within the CGP function set could be beneficial and was demonstrated by repeating the earlier 4-bit multiplier experiment with the addition of a loop function.
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Transport Triggered Architecture

The transport triggered architecture (TTA) was created in the 1980's, as a development of the Very Long Instruction Word (VLIW) architecture (Corporaal, 1998). The TTA usually contains an instruction decoder, an interconnection network and a number of functional units (FU), as shown in Figure 1. Functional units and the decoder are connected through data and address buses. A single data/address bus pair is called a slot. A processor can have multiple slots to allow parallelism. An input/output interface of a functional unit is called a port. Ports are usually globally addressable. The connection of a port to a slot is called a socket and the number of conjunctions in a socket is flexible.

Figure 1.

Transport triggered architecture (Mudry, 2009)

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