Design and Development of a Parallel Lexical Analyzer for C Language

Design and Development of a Parallel Lexical Analyzer for C Language

Swagat Kumar Jena (Gandhi Institute of Technological Advancement, Department of Computer Science and Engineering, Bhubaneswar, India), Satyabrata Das (VSS University of Technology, Department of Computer Science and Engineering, Burla, India) and Satya Prakash Sahoo (VSS University of Technology, Department of Computer Science and Engineering, Burla, India)
Copyright: © 2018 |Pages: 15
DOI: 10.4018/IJKBO.2018010105
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Abstract

Future of computing is rapidly moving towards massively multi-core architecture because of its power and cost advantages. Almost everywhere Multi-core processors are being used now-a-days and number of cores per chip is also relatively increasing. To exploit full potential offered by multi-core architecture, the system software like compilers should be designed for parallelized execution. In the past, various significant works have been made to change the design of traditional compiler to take advantages of the future multi-core platform. This paper focuses on adapting parallelism in the lexical analysis phase of the compilation process. The main objective of our proposal is to do the lexical analysis i.e., finding the tokens in an input stream in parallel. We use the parallel constructs available in OpenMP to achieve parallelism in the lexical analysis process for multi-core machines. The experimental result of our proposal shows a significant performance improvement in the parallel lexical analysis phase as compared to sequential version in terms of time of execution.
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Multi-Core Architecture

A Multi-core processor is an integrated circuit die (known as a chip multiprocessor or CMP) with two or more independent actual central processing units called “cores”. Each processor has its own primary cache and pipelined. The multiple cores processors can run multiple instructions at the same time, increasing the overall execution speed for programs which yields to parallel computing. Now-a-days almost all high-performance processors are belonging to multi-core family. While it is generally accepted that we have entered the multi-core era, but still researchers are concerned on scaling and adapting software to multi-core platform.

Some examples of multi-core processors are as follows; Intel Pentium D, Dual Core Opteron, Intel Montecito, Intel Xeon E7-2820 with 8 cores, Sun UltraSPARC IV, IBM Cell, Intel WoodcrestIBM Power4, IBM Power, AMD Quad- and Dual-Core UltraSPARC T1, AMD FX-8150 with 8 cores,Adapteva Epiphany with up to 4096 processors on-chip, SEAforth 40C18, a 40-core processor by IntellaSys etc. This represents the scalability of multi-core architecture.

Figure 1 shows a multi-core architecture with two nodes. One node is based on Non-Uniform Memory Access (NUMA) based design and other is based on Symmetric Multi-Processing (SMP) based design. In NUMA memory access times of cores can be different where as in SMP memory access times of cores are similar. Each core has similar structure in both nodes and has its private L1 cache. Two nodes can be connected through interconnection network like mesh, bus, and ring network.

Figure 1.

This figure shows multi-core architecture with two nodes. One node is based on NUMA (Non-Uniform Memory Access) based design and other one is based on SMP (Symmetric Multi-Processing) based design, two nodes can be connected through interconnection network.

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