Investigating Power Reduction for NoC-Based Spiking Neural Network Platforms using Channel Encoding

Investigating Power Reduction for NoC-Based Spiking Neural Network Platforms using Channel Encoding

Neil McDonnell (School of Computing and Intelligent Systems, University of Ulster, Magee Campus, Northern Ireland, UK), Snaider Carrillo (School of Computing and Intelligent Systems, University of Ulster, Magee Campus, Northern Ireland, UK), Jim Harkin (School of Computing and Intelligent Systems, University of Ulster, Magee Campus, Northern Ireland, UK) and Liam McDaid (School of Computing and Intelligent Systems, University of Ulster, Magee Campus, Northern Ireland, UK)
DOI: 10.4018/jaras.2012100101
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Abstract

Recent focus has been placed on exploring the possibility to switch from parallel to serial data links between NoC routers in order to improve signal integrity in the communication channel. However, moving streams of data between the parallel path of the internal router and external serial-channel links between them consumes additional power. One challenge is encoding the data and minimise the switching activity of data in the serial links in order to reduce the additional power dissipation; while under real-time and minimal hardware constraints. Consequently, proposed is a novel low area/power decision circuit for NoC channel encoding which identifies in real-time packets for encoding and extends the existing SILENT encoders/decoders to further minimise power consumption and demonstrates the power performance savings of the decision circuit and modified (en)decoders using example test traffic with the EMBRACE NoC router, a mixed signal spiking neural network (SNNs) embedded platform.
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Introduction

Intelligent system design uses biologically inspired computational models in an attempt to replicate the immense processing power of the brain. For centuries scientists have carefully studied the brain using a variety of methods in an attempt to gain a deeper understanding of its functionality and elegance. As technology has advanced over the last century, scientists have been able to uncover new information on the structure of the brain leading to the development of more accurate and powerful simulation models. The basic information processing element of the human brain is the neuron of which there are an estimated 100 billion (Arbib et al., 2002), and are interconnected based on complex network structures. These dense, highly interconnected networks of neurons are very energy-efficient and robust at processing information, and are responsible for numerous functions from decision making to processing sensory inputs. Spiking neural networks (SNNs) aim to mimic the way neurons communicate in nature and emulate the complex neural networks found in biology (Gerstner et al., 2002). Researchers seek to use SNNs to harness the large scale efficient processing capabilities of the biological brain and build hardware computing platforms that realise large scale SNNs paradigms (Furber et al., 2007; Harkin et al., 2009; Merolla et al., 2011; Philip et al., 2009).

Current software environments for simulating SNN models are found to have limitations (de Garis et al., 2010). Running large network simulations can be time consuming as biological systems are inherently parallel and traditional computing architecture such as Von Neumann is sequential (Pande et al., 2007). Additionally as networks increase in size, more and more processor cores are required. This results in a significant increase in power requirements and more complex interconnections (Maguire et al., 2007). One solution to the scalability challenges for SNNs in hardware is the EMBRACE architecture which utilise Networks-on-Chip (NoC) and custom low-powered neurons/synapse to build hardware implementations. The NoC in particular provides scalable interconnectivity where significantly large numbers of neurons can be connected in hardware. An example of this can be found in the EMBRACE architecture, recently proposed by the authors in (Harkin et al., 2009; Cawley et al. 2011).

The main components of the NoC interconnect paradigm are routers, network interfaces and multiple parallel channel links between routers. The routers provide the on-chip communication infrastructure for embedded systems, implementing a similar hardware concept to that found in common computing networks (Dally et al., 2004; Benini et al., 2002). For example, multiple packets of data are transmitted simultaneously from multiple sources to multiple destinations across a shared network of NoC routers. It should be noted that even though the computer network was the initial inspiration for the NoC interconnect paradigm, the traditional computer network methods and algorithms cannot be applied directly into the NoC paradigm (Benini & De Micheli, 2002) as the NoC imposes specific constrains in terms of area utilisation and power consumption, which are not a main concern for traditional network computer applications. The aforementioned constrains are imposed due to the requirement to implement the NoC on embedded hardware.

Nowadays, as device technology sizes shrink and NoC network sizes increase, the power dissipated by the parallel channel links of the routers become as important to the overall system as the routers and network interfaces (Carrillo et al., 2010). More importantly, with the large number of parallel data lines per channel, the router links become more susceptible to loss of signal integrity due to crosstalk (Pande et al., 2007), and it becomes very challenging to synchronise transmissions with increasing clock frequencies (Kangmin et al., 2004). This results in unreliable communication channels and becomes more pronounced for large scale systems. Serialising data links between routers can address these issues, for example, the likelihood of crosstalk can be reduced by reducing the number of parallel lines and increasing the spaces between links (Morgenshtein et al., 2004; Suutari et al., 2001). However, this has an impact on the maximum throughput of a channel as data is transmitted serially instead of parallel, as a trade-off is made for increased reliability. Nevertheless, reduced throughput can be minimised with increased transmission clock speeds.

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