Performance Analysis of Temperature Management Approaches in Networks-on-Chip

Performance Analysis of Temperature Management Approaches in Networks-on-Chip

Tim Wegner (University of Rostock, Rostock-Warnemuende, Germany), Martin Gag (University of Rostock, Rostock-Warnemuende, Germany) and Dirk Timmermann (University of Rostock, Rostock-Warnemuende, Germany)
DOI: 10.4018/jertcs.2012100102

Abstract

With the progress of deep submicron technology, power consumption and temperature related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management. On the other hand, application of thermal management is accompanied by disturbance of system integrity and degradation of system performance. In this paper the authors propose to precompute and proactively manage on-chip temperature of systems based on Networks-on-Chip (NoCs). Thereby, traditional reactive approaches, utilizing the NoC infrastructure to perform thermal management, can be replaced. This results not only in shorter response times for application of management measures and a reduction of temperature and thermal imbalances, but also in less impairment of system integrity and performance. The systematic analysis of simulations conducted for NoC sizes ranging from 2x2 to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile.
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Introduction

The emergence of nanotechnology is accompanied by cumulative power densities and switching activities per unit area. Therefore, increasingly complex and highly integrated systems like SoCs have to contend with well-known challenges. Amongst others, this concerns heat dissipation, leading to high circuit temperatures and possibly strongly unbalanced on-chip temperature distributions (see ∆T [°C] in Table 7 for examples regarding on-chip temperature variations). In the light of a growing number of transistors per chip, which are increasingly susceptible to environmental influences and deterioration, this issue is topical more than ever. As a consequence, thermal stress and physical effects exponentially depending on temperature (JEDEC, 2009) threaten the integrity of Integrated Circuits (ICs) and have major influence on operability, lifetime and performance. The relationship between temperature and deterioration is illustrated by the Arrhenius model (Srinivasan & Adve, 2003) describing the influence of temperature on the velocity of chemical reactions. This model originates from the Van’t Hoff rule also known as the reaction rate temperature rule (or RGT rule), saying that chemical reactions take place twice as fast when temperature is increased by 10 K. As a rule of thumb, this also can be interpreted as a bisection of lifetime of ICs with every 10 K temperature increase. For this reason, monitoring and control of on-chip temperature distribution are important tasks to secure system functionality and ensure high performance.

Table 7.
Router delay DR, Delay of Packet delivery DP, net data throughput DataNet, the number of delivered packets PTrans, average temperature TAvg, the peak temperature difference ∆T and the average time a router operated in unsafe temperature state tR,illegal for the reference system
Reference2x23x34x4
DR [cycles]566
DP [cycles]293441
DataNet [bit/cycle]3376142
PTrans2949522678925012685515
TAvg [°C]66.569.772.9
∆T [°C]12.130.639.2
tR,illegal [ms]33.237.241.5

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