Discrete Event Simulation Process Validation, Verification, and Testing

Discrete Event Simulation Process Validation, Verification, and Testing

Evon M. O. Abu-Taieh (The Arab Academy for Banking and Financial Sciences, Jordan) and Asim Abdel Rahman El Sheikh (The Arab Academy for Banking and Financial Services, Jordan)
Copyright: © 2007 |Pages: 36
DOI: 10.4018/978-1-59140-851-2.ch008
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Abstract

This chapter introduces validation, verification, and testing tools and techniques pertaining to discrete event simulation. The chapter distinguishes between validation and verification within the context of discrete event simulation. Then, we will show the importance of such topic by revealing the amount research done in simulation validation and verification. The chapter subsequently discusses the reasons why simulation projects fail and the sources of simulation inaccuracies. Next, the chapter gives different taxonomies for validation, verification, and testing techniques (VV&T) for both types of simulation systems: object-oriented-based and algorithmic-based. Therefore, the chapter will present a translation of thirteen software-engineering practices suggested for simulation projects. Notwithstanding the significance of providing an objective assessment platform, as such, the chapter will shed light on the independence of VV&T pertaining to simulation systems.

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