This chapter focuses on the future and present state of art relating to microwave diplexer design. It particularly highlights the future opportunities in making improvements in the diplexer design process, in order to achieve better miniaturised diplexer components. The ideas discussed in this chapter could be futher investigated by researchers, including postgraduate students pursuing Master of Science (i.e. M.Sc.) and/or Doctor of Philosophy (i.e. Ph.D.) degrees. The chapter briefly discussed some varients of the SIW transmission line technology including the half-mode substrate integrated waveguide (HMSIW), and the folded substrate integrated waveguide (FSIW).
State of the Art
This book has presented a design procedure of a microwave diplexer circuit without the need for using neither an external non-resonant junction, nor an out of band common resonator. The absence of both a non-resonant external junction and an out of band common resonator in the designed circuit model, means that the resultant diplexer is relatively small in size when compared to conventional diplexers that depend on T or Y non-resonant junctions or an out of band common resonator for energy distribution. The diplexer design technique presented in this book is exploiting on well-known formulations for achieving bandpass and dual-band bandpass filters, hence, results in simple design with reduced uncertainties.
The design was initially implemented using asynchronously tuned microstrip square open-loop resonators, where the simulation and measurement results show that an isolation of 50 dB was achieved between the diplexer transmit and receive channels. A minimum insertion loss of 2.88 dB for the transmit band, and 2.95 dB for the receive band, were also achieved in the microstrip diplexer. The design was also implemented using the SIW technique, where the insertion loss of 2.86 dB and 2.91 dB were achieved across the transmit and the receive channels of the SIW diplexer, respectively. The simulation for both the microstrip and the SIW diplexers were based on ideal loss conditions, i.e. the surface roughness and the thickness variation of the substrate were not considered.
This book has recommended the use of polygons in place of the conventional circular metallic posts in the simulation phase. This is a way of reducing simulation time to up to 300% as explained in chapter 3. However, care must be taken when deciding on the number of sides the polygon must have for best results comparison between simulated and measured components. As explained in Chapter 3, using fewer sided polygons will achieve the fastest simulation time, but will cause an enormous frequency shift to the left (i.e. reduction in the centre frequency of the component). Based on the results shown in Chapter 3, figure 35, a recommendation of 10 or more side polygons as metallic posts should be used to achieve good simulation results with improved simulation time of up to 300%. Using fewer side polygons in lieu of the circular metallic posts will also degrade the return loss of the component being simulated as shown in chapter 3, figure 35.
This book also discusses the implementation of a new type of SIW transition technique that was first demonstrated in a 3-pole bandpass filter (Nwajana et al., 2017). The Microstrip-CPW-SIW transition technique exploited the step impedance between a 50 Ohms input/output feedline to control the input/output coupling of the filter. The minimal milling or etching requirements of the SIW ensured that fabrication errors were kept at the barest minimum. Both the SIW bandpass filter and the SIW diplexer presented were fabricated using the low cost and commercially available PCB technology. The micro-milling process was performed on the LKPF Protomat C60 which is a cheap alternative to photolithography.