High-Speed Logic Level Fault Simulation

High-Speed Logic Level Fault Simulation

Raimund Ubar (Tallinn University of Technology, Estonia) and Sergei Devadze (Tallinn University of Technology, Estonia)
Copyright: © 2011 |Pages: 28
DOI: 10.4018/978-1-60960-212-3.ch014
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In the first part of the chapter, an introduction to the problem of logic level fault simulation is given together with the overview of existing fault simulation techniques. The remaining part of the chapter describes a new approach to fault simulation based on exact critical path tracing to conduct fault analysis in logic circuits. A circuit topology driven computational model is presented which allows not only to cope with complex structures of nested reconvergent fan-outs but also to carry out the fault reasoning for many test patterns concurrently. To achieve the speed-up of backtracing, the circuit is simulated on higher than traditional gate level. As components of the circuit network, fan-out free regions of maximum size are considered, and they are represented by structurally synthesized BDDs. The latter allow to reduce the number of internal variables in the computation model, and therefore to process the whole circuit faster than on the flat gate-level. The method is explained first, for the stuck-at fault model, and then generalized for an extended class of functional fault model covering the conditional stuck-at and transition faults. The method can be used for simulating permanent faults in combinational circuits, and transient or intermittent faults both in combinational and sequential circuits with the goal of selecting malicious faults for injecting into fault tolerant systems to evaluate their dependability. Experimental results are included to give an idea how efficiently the method works with different fault classes.
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Fault simulation is a central task in digital testing used for estimating the quality of tests for digital circuits. In addition, the procedure of fault simulation is often required for other test related tasks like fault diagnosis, automated test pattern generation (ATPG), test compaction, built-in self test optimization, design of reliable systems and others. It makes the performance of a fault simulator be a key factor for improving the efficiency of solving all the above mentioned tasks.

In contrast with logic simulation (fault-free, true-valued), the goal of fault simulation is to evaluate the behavior of a circuit in case of presence of faults inside it. In particular, the fault simulator has to find out whether the output response of a circuit is changing due to the influence of a fault or not. A fault, which effect propagates to primary outputs or scan-path flip-flops under the current test pattern, is referred as detected by this pattern. The task of the fault simulator is to determine which faults could be discovered by applying the given test stimuli. The ultimate result of fault simulation is the measurement of the effectiveness of test patterns to detect the faults.

In this chapter we consider logic circuits. The higher than logic level fault simulation methods are discussed in other chapters of the book (Misera, and Urban, 2010; Ubar, Raik, & Jenihhin, 2010; Raik et al. 2010). The main discussion is carried out for simulating permanent faults in combinational and full scan-path circuits. However, the results presented are easily extendable for simulating permanent faults in sequential circuits without global loops, and for simulating transient or intermittent faults in logic level sequential circuits with global feedbacks. The latter case is important for dependability analysis of systems, where the goal is to select malicious faults for injecting them into fault tolerant systems for evaluating the efficiency of fault-tolerant mechanisms.

Fault simulator typically works with a specific fault model. Stuck-at fault (SAF) model is the most commonly used in digital testing. The presence of a SAF in a digital circuit permanently fixes the value of the corresponding signal line to logic one (stuck-at 1, SA1) or logic zero (stuck-at 0, SA0). Although a SAF can be straightforwardly interpreted as a short between signal net and ground (or power) line, many other defects manifest themselves also as SA0 or SA1. Typically, single SAF model is used, which assumes occurrence only of a single stuck-at fault in the circuit under test (CUT). This restriction helps to reduce the total number of considered faults to 2v (where v is the number of circuit lines). The experiments have shown that 100% coverage of single faults detects the most of multiple faults as well (Agarwal, & Fung, 1981; Bushnell, & Agrawal, 2000).

Moreover, even in the case of single-fault assumption not all the faults have to be considered. For instance, two different faults could affect circuit in the exactly same way, i.e. be indiscriminate. Certainly, the processing of both such faults is redundant, thus one of them could be dropped out of the list of faults to be considered. The well-known technique of reduction of the complete list of faults without losing the quality of defect coverage is called fault collapsing (Abramovici, Breuer & Friedman, 1990).

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