This chapter represents some essential aspects of nanowires and their transport properties. Scaling of MOSFETs becomes a huge problem for industries due to short channel effects (SCEs) and sub-threshold leakage current. So, nanowires become a good solution to SCEs due to their structure. This chapter is divided into three parts. The first part gives a brief introduction of nanowire and different materials that can replace Si (channel material) and SiO2 (oxide material) due to their superior performance over Si. In the second part, the device structure and device structural measurement is discussed. In the third part, transport properties are discussed. This chapter shows the behavior of nanowire on changing different device materials and device dimensions. Electrical characteristics of Si and III-V based nanowires FETs will be analyzed and compared. High-k dielectric as oxide material also helps in improving device performance. HfO2 shows improvement in device characteristics over SiO2 taken as an oxide material. Junctionless nanowire MOSFET has also been designed and analyzed.
TopIntroduction
Electronic devices are an essential part of today’s life. It is hard to think, construct an electronic device without complementary metal oxide semiconductor (CMOS) technology. CMOS technology has played an important role in the integrated circuit industry. According to CMOS technology, device size can be reduced by increasing on-chip transistors with every generation. Tapered device ensures improved performance, high drivability and increased speed. And also reduce cost and packaging density (Neamen, 2012)(Sze & Lee, 2008)(Kim, 2010)(Larson & Snyder, 2006). This minimization of device is known as scaling and this downscaling is done by following Moore’s law (Kim, 2010). Now the device scaling reached in nanometer regime, a number of problems obstruct normal behaviour of MOSFETs. Short channel effects are introduced due to reduced size which increases threshold voltage because of two dimensional (2D) electrostatic charge confinements in the active region (channel) of the MOSFET(Gupta, 2018)(Young, 1989). Due to increment in threshold voltage, power consumption also increased. Due to reduced gate length heat generation is high due to increased power consumption at high- frequency operations. Power consumption can be reduced by lowering supply voltage which results in less operational speed of MOSFETs. So power management becomes a big task during scaling of MOSFETs. Short channel requires ultra-shallow junction(Skotnicki et al., 2005) (Nader Shehata et al., 2015)(Division et al., 2014)(P. Razavi et al., 2011) formation which is a great challenge for fabrication labs.
Downscaling of MOSFETs is the most effective way to enhance performance as well as current density of the device [16]. To extend Moore’s law further chip density should be increased to enhance operating speed of device which can be achieved by reducing the size of device (Sze & Lee, 2008)(Kim, 2010). Reduction in channel length introduce some short channel effects(SCEs) like DIBL, hot carriers, velocity saturation etc.(Bradley et al., 2003). Further scaling of conventional MOSFET becomes a huge challenge due to the formation of the junctions in the device (Division et al., 2014)(P. Razavi et al., 2011). The introduction of multigate devices becomes a necessity to overcome issues like SCEs, leakage current. MOSFET with different device geometry like Double gate, Tri gate, SOI (Silicon on Insulator) MOSFET, Fin FET and with different mechanism like junctionless MOSFET were designed to improve performance of device. In double gate MOSFETs, presence of two gates (top gate and bottom gate) makes strong control over the channel region through the both gates and leads to reduction in SCEs of device. Doubling of gate to channel coupling helps in SCEs reduction (Wong et al., 1997)(Rahman & Lundstrom, 2002). Further scaling of device is also possible by using DG-MOSFET and also number of transistor per chip can be increased. DG-MOSFET provide decrease in threshold voltage, good carrier mobility of electrons, better switching property in the device, small leakage and near ideal sub-threshold slope with less power consumption (Tsormpatzoglou et al., 2008)(Wu et al., 2013) (Jiang et al., 2015).
Trigate MOSFETs consists of three gates placed around the channel region. The gates are placed on both sides as well as top of MOSFET. Scaled gate length results in SCEs enhancement with high controllability of gate over channel region. In Trigate MOSFET, three gates are fabricated around the channel to increases the gate controllability. The presence of the three gates allows the electrons to travel on three-time enhanced surface area. Trigate MOSFET reduces leakage current and consumes less power than the conventional MOSFET (Nirmal et al., 2013) (Holtij et al., 2015)(Ávila-Herrera et al., 2016).
Parasitic capacitance is also an important factor which effects device performance. Silicon on insulator (SOI) MOSFET technology resolves parasitic capacitance issue by utilizing layered silicon–insulator–silicon substrate instead of conventional silicon substrate during semiconductor fabrication. Layered silicon helps in parasitic capacitance reduction which improves speed of the device [6]. The implementation of SOI technology allows further downscaling in the device. SOI MOSFET provides many advantages over the conventional MOSFET such as device with lower parasitic capacitance due to substrate isolation, less power consumption due to lower parasitic capacitance, higher performance. Isolation from the substrate also gives advantage of high power efficiency with lower leakage current (J. P. Colinge, 2008)(Chaudhry & Kumar, 2004)(Reddy et al., 2005).