Low Power VLSI Circuit Design using Energy Recovery Techniques

Low Power VLSI Circuit Design using Energy Recovery Techniques

V. S. Kanchana Bhaaskaran (VIT University, India)
Copyright: © 2016 |Pages: 37
DOI: 10.4018/978-1-5225-0190-9.ch006
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With the rapidly evolving silicon technology, the power density becomes increasingly high. Quadratically related to power, the voltage scaling offers a means of minimizing energy. However, power supply scaling demands less threshold voltage, which rises leakage current. Several low power techniques have been devised. This chapter deals with the non-conventional low power design solutions, based on adiabatic switching theory. In such circuits, the energy rather than getting dissipated during every cycle, is transferred back and forth between the logic and power-clock sources. A brief discussion on the reversible logic circuits will be presented followed by the fully adiabatic and quasi-adiabatic circuits. The use of power-clock sources for operating the adiabatic circuits will also be introduced. The generalized energetics of an adiabatic circuit followed by the typical loss models of the adiabatic families are presented. Some of the adiabatic circuits employing CMOS transistors are introduced in the chapter. A short comparison for the adiabatic circuit leakage models follows.
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Need for Low Power

With the rapid evolution in silicon technology, the transistor size continues decreasing remarkably, and the chips grow up in functionality with the switching frequencies increasing in parallel. The power dissipation in the chip thus becomes increasingly high. In 1980s, the growing power dissipation in the microprocessors, the memory and a multitude of ASICs prompted an industry-wide shift from the bipolar and NMOS technologies to CMOS to assuage the problem of heat dissipation. This attempt greatly reduced the average power dissipation resulting in a provisional solution. However, higher packing densities necessitated during the 1990s brought in the requirement for low power design methodologies to the fore. While the design parameters were performance and area previously, power was recognized in 1990s. Presently, the power management of integrated circuits has attained the primary status and proves one of the most important performance metrics for SoCs than the throughput, latency or frequency.

The need for low power operation arises for the following reasons:

  • 1.

    Low power computing applications are small systems, where battery weight is crucial. The battery technology does not advance in line with the portable systems of high performance and complexity, and its energy density improves only by about 6% annually.

  • 2.

    Large and high performance systems require huge power and necessary cooling.

  • 3.

    The environmental concerns insist low power design with electricity generation being a major source of air pollution.

Thus, it can be concluded that designing power efficient electronic systems design is more prudent than the research on power generation itself.


Conventional Methodologies Of Low Power Vlsi Design And The Current Status

The commonly used three degrees of freedom available in the low-power design arena are the supply voltage, the switched capacitance and the switching activity. Being quadratically related to power, voltage reduction directly offers a means of minimizing the energy consumption. However, an unrelenting voltage reduction demands appropriate reduction in threshold voltage across each technology node resulting in increasing leakage and this makes it harder to continue voltage scaling envisaged as shown in Figure 1(a)(Piguet, 2007). The reduction of the supply voltage leads to reduced speed performance also. The energy consumed per logic operation does not drop as it had been occurring with older technologies as shown in Figure 1(b) with the energy required per operation saturating beyond 130 nm. Additionally, the low voltage operation makes the threshold voltage characteristics more vulnerable to temperature variations.

Figure 1.

(a) Supply voltage scaling and (b) Energy per logic operation across technology generations


The transistors working at GHz frequencies suffer from exponentially increasing leakage. It is more difficult to scale Vdd down than the other parameters. This is mainly due to the fundamental limit of the threshold slope of approximately 60mV/decade. It can be more severe when supply voltage reaches down to 0.6V. International Technology Roadmap of Semiconductors (ITRS) (ITRS, 2013) finds that the rising dynamic power density per unit area will sooner than later reach an acceptable level. On the other hand, the static power dissipation is expected to become more difficult to control, while working for high performance as the target. Hence, the ITRS report given in Table 1 foresees that the innovations in circuit design and architecture for performance and power management are imperative. This includes parallelism for improved performance at the cost of increased transistor count and silicon area, and aggressive design of power gating the circuits. A trade-off between speed performance and other factors, namely, lower leakage current or low standby power, device count and chip area is the goal of low power solutions.

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