A Neuromorphic Single-Electron Circuit for Noise-Shaping Pulse-Density Modulation

A Neuromorphic Single-Electron Circuit for Noise-Shaping Pulse-Density Modulation

Andrew Kilinga Kikombo (Hokkaido University, Japan), Tetsuya Asai (Hokkaido University, Japan), Takahide Oya (Yokohama National University, Japan), Alexandre Schmid (Swiss Federal Institute of Technology (EPFL), Switzerland), Yusuf Leblebici (Swiss Federal Institute of Technology (EPFL), Switzerland) and Yoshihito Amemiya (Hokkaido University, Japan)
DOI: 10.4018/978-1-60960-186-7.ch010
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Abstract

We propose a bio-inspired circuit performing pulse-density modulation with single-electron devices. The proposed circuit consists of three single-electron neuronal units, receiving the same input and are connected to a common output. The output is inhibitorily fedback to the three neuronal circuits through a capacitive coupling. The circuit performance was evaluated through Monte-Carlo based computer simulations. We demonstrated that the proposed circuit possesses noise-shaping characteristics, where signal and noises are separated into low and high frequency bands respectively. This significantly improved the signal-to-noise ratio (SNR) by 4.34 dB in the coupled network, as compared to the uncoupled one. The noise-shaping properties are as a result of i) the inhibitory feedback between the output and the neuronal circuits, and ii) static noises (originating from device fabrication mismatches) and dynamic noises (as a result of thermally induced random tunneling events) introduced into the network.
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Introduction

For the past 3 decades, the scaling of semiconductor devices has been the primary driving force behind improving the performance of LSI processors and systems. The decreasing feature sizes of transistors have been accompanied by dramatic increase in speed and integration densities, which have in turn led to increased and diversified functionality. This trend has been viable mainly due to guaranteed reliability in the downscaled devices even with decreasing process technologies. Reliability corresponds to high yields per die, hence low production costs (high cost efficiency), giving the circuit designer the opportunity to create reliable integrated systems with improved processing speeds, and increased functionality.

However, as the physical feature sizes approach the deep sub-micron regime, process variations and undesirable internal (and or external) noises associated with nano-scale properties pose critical concerns in the future of scaling and in system system design; they dramatically reduce the reliability of electronic devices on the edge of the nano-scales (Bowman, 2002; Constantinescu, 2003; Jose, 2003; Way & Taeho, 1999). This reduced reliability is even more conspicuous as electronic device sizes are further scaled down to the nano-meter regime (Calhoun, 2008; Orshansky, 2002; Stolk, 1998).

Getting rid of these nano-scale characteristics would involve introducing error-detecting circuits within the system, which leads to advanced complexity, and design tradeoffs in using high integration capacities available to the circuit designer. Some design techniques offering possible ways to mitigate the impact of within-die variations have been explored (Marculescu & Talpes, 2005; Tiwari, 2007). Other works involving introducing error-detecting circuitry in electronic systems include architectures proposed by Milor (1989) and Chatterjee (1993). Unfortunately, these approaches offer only a short term solution. The uncertainty in coming up with a long-lasting solution to these challenges has paved the way into a new field of the so called emerging research nano devices, which effectively utilize nano-scale characteristics in their operation. Such devices are viewed as promising blocks for creating application-specific processors, and ultra low-power systems in coming generations of LSI platforms. Such devices would include single-electron devices (Grabert & Devoret, 1992; Nakajima, 1997).

Single-electron devices inherently operate with extreme low power dissipation, and provide a high integration density per unit area. Thus, they are viewed as potential building blocks for low-power, parallel-based computational applications in future LSI platforms. However, one of the major problems facing single-electron devices is that they are potentially unreliable. Their low reliability originates from two factors: i) large variations in the features of fabricated devices, hence device characteristics, and ii) sensitivity to internal and external noises. Therefore, despite all the appealing features in utilizing nano-electronic devices in future electronic systems, we have to address and solve a fundamental question; how do we build reliable systems from error-prone building devices?

Improvements in fabrication technology alone cannot accomodate such enormous device failures. Therefore in designing functional electronic devices in the deep sub-micron and post-silicon era, we need to keep in mind the fact that we have to build reliable systems with unreliable (ITRS, 2005), and error-prone devices (Nikolic, 2001; Schimid & Leblebici, 2004; Goser, 1997). Thus the need to address robustness and design systems with large enough signal-to-noise ratio is inevitable (Hamed, 1997).

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