System-Level Design of NoC-Based Dependable Embedded Systems

System-Level Design of NoC-Based Dependable Embedded Systems

Mihkel Tagel (Tallinn University of Technology, Estonia), Peeter Ellervee (Tallinn University of Technology, Estonia) and Gert Jervan (Tallinn University of Technology, Estonia)
Copyright: © 2011 |Pages: 36
DOI: 10.4018/978-1-60960-212-3.ch001
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Abstract

Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication problems and to address dependability at various levels of abstraction. This chapter concentrates on system-level design issues of NoC-based systems. It describes various methods proposed for NoC architecture analysis and optimization, and gives an overview of different system-level fault tolerance methods. Finally, the chapter presents a system-level design framework for performing design space exploration for dependable NoC-based systems.
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In this section we first describe the design challenges that have emerged together with the technology scaling and due to increase of the design complexity. We give an overview of the key concepts and NoC terminology. The second part of this section is devoted to system-level design and dependability issues.

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